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參數(shù)資料
| 型號(hào)： | XRT7245 |
| 廠商： | Exar Corporation |
| 英文描述： | DS3 ATM User Network Interface(DS3異步傳輸模式用戶網(wǎng)絡(luò)接口) |
| 中文描述： | DS3自動(dòng)柜員機(jī)用戶網(wǎng)絡(luò)接口（DS3異步傳輸模式用戶網(wǎng)絡(luò)接口） |
| 文件頁(yè)數(shù)： | 18/324頁(yè) |
| 文件大小： | 4103K |
| 代理商： | XRT7245 |
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XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
18
86
RLOS
I
Receive LOS (Loss of Signal) Indicator Input (from XRT7295 DS3 Line Receiver).
This input pin is intended to be connected to the RLOS (Receive Loss of Signal) output
pin of the XRT7295 DS3 Line Receiver IC. The user can monitor the state of this pin by
reading the state of Bit 0 (RLOS) within the Line Interface Scan Register (Address = 73h).
If this input pin is “l(fā)ow”, then it means that the XRT7295 device is detecting a sufficient
amount of signal energy on the line, due to the incoming DS3 data-stream. However, if this
input pin is “high”, then it means that the XRT7295 device is not detecting a sufficient
amount of signal energy on the line, due to the incoming DS3 data-stream, and may
be experiencing a “Loss of Signal” condition.
For more information on the operation of the XRT7295 DS3 Line Receiver IC, please
consult the “XRT7295 DS3 Integrated Line Receiver” data sheet.
Note:
Asserting the RLOS input pin will cause the XRT7245 DS3 UNI device to
declare an “LOS” (Loss of Signal) condition. Therefore, this input pin should not be
used as a general purpose input.
87
8KRef
I
8 kHz Reference Clock Input for the PLCP Processors:
The Transmit PLCP pro-
cessor can be configured to synchronize its PLCP frame processing to this clock sig-
nal. The Transmit PLCP Processor will also use this signal to compute the trailer
nibble stuff opportunities.
Note:
This input signal is active only if the user has configured the PLCP Processors
to use this signal as their “master clock” signal. The user can configure the UNI to use
this signal by setting TimRefSel[1,0] (within the UNI Operating Mode Register) to 01.
88
RxLOS
O
Receive DS3 Framer—Loss of Signal Output Indicator:
This pin is asserted when
the Receive DS3 Framer encounters 180 consecutive 0’s via the RxPOS and RxNEG
pins. This pin will be negated once the Receive DS3 Framer has detected at least 60
“1s” out of 180 consecutive bits.
89
RxOH
O
Receive DS3 Framer Overhead Bit Serial Output pin:
This output pin, along with
RxOHClk and RxOHFrame, combine to form the “Receive DS3 Framer OH Bit” Serial
output port. The UNI Receive DS3 Framer will extract the overhead bits from the incom-
ing DS3 signal, and serially output these bits on this output pin on the rising edge of
the RxOHClk output signal.
90
RxOOF
O
Receiver DS3 Framer—“Out of Frame” Indicator:
The UNI Receive DS3 Framer will
assert this output signal whenever it has declared an “Out of Frame” (OOF) condition
with the incoming DS3 frames. This signal is negated when the framer correctly
locates the F- and M-bits and regains synchronization with the DS3 frame.
91
GND
***
Ground Signal Pin
92
RxAIS
O
Receive “Alarm Indication Signal” Output pin:
The UNI will assert this pin to indi-
cate that the Alarm Indication Signal (AIS) has been identified in the Receive DS3
data stream. An “AIS” is detected if the payload consists of the recurring pattern of
1010... and this pattern persists for 63 M-frames. An additional requirement for AIS
indication is that the C-bits are set to 0, and the X-bits are set to 1. This pin will be
negated when a sufficient number of frames, not exhibiting the “1010...” pattern in the
payload has been detected. For more details, please see Section _.
93
RxOHClk
O
Receive DS3 Framer Overhead Bits Serial Output Port Clock.
This pin, along with
the RxOH and RxOHFrame pins function as the “Receive DS3 Framer Overhead bit”
serial output port. This pin functions as a clock signal that can be used by external cir-
cuitry to latch and process the serial data from the RxOH pin.
94
RxPFrame
O
PLCP Frame Boundary Indicator Output—Receive PLCP Processor.
This output
pin pulses “high” when the Receive PLCP Processor is receiving the last bit of a PLCP
frame.
PIN DESCRIPTION (CONT’D)
P
IN
N
O
.
S
YMBOL
T
YPE
D
ESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT7288IP | CEPT1 Line Interface |
| XRT7288 | CEPT1 Line Interface(CEPT1線接口) |
| XRT7288IW | CEPT1 Line Interface |
| XRT7295AE | E3 (34.368Mbps) Integrated line Receiver |
| XRT7295AE_03 | E3 (34.368Mbps) Integrated line Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7250 | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/E3 FRAMER IC |
| XRT7250ES-PCI | 功能描述:界面開(kāi)發(fā)工具 Evaluation Board for XRT7250 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XRT7250IQ100 | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/E3 FRAMER IC |
| XRT7288 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CEPT1 Line Interface |
| XR-T7288 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CEPT1 Line Interface |
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