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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
XVII
An Advisory to Users .................................................................................................................................. 273
Receive UTOPIA FIFO Manager Features and Options ........................................................................... 274
UTOPIA Configuration Register: Address = 6Ah ...................................................................................... 276
Receive UTOPIA—Interrupt/Status Register (Address—6Bh) ................................................................ 277
Receive UTOPIA FIFO Status Register (Address = 6Dh) ......................................................................... 277
RxFIFO Full .................................................................................................................................................. 277
Rx FIFO Empty ............................................................................................................................................. 278
UTOPIA Configuration Register: Address = 6Ah ...................................................................................... 278
Final Comments on Single-PHY Mode ...................................................................................................... 282
Receive UTOPIA Address Register: (Address = 6Ch) .............................................................................. 282
Tx UTOPIA Address Register (Address = 70h) ......................................................................................... 282
Polling Operation ......................................................................................................................................... 284
The ATM Layer Processor’s Role in the “Polling” Operation ......................................................................... 284
The UNI Device’s Role in the “Polling” Operation ......................................................................................... 284
UNI Interrupt Status Register (Address = 05h) ......................................................................................... 287
Address = 6Bh, Rx UT Interrupt Enable/Status Register ......................................................................... 287
Bit 0–—RCOCA Interrupt Status—Receive UTOPIA Change of Cell Alignment Condition .................. 288
Address = 6Bh, Rx UT Interrupt Enable/Status Register ......................................................................... 288
Bit 1—Rx FIFO Underflw Interupt Status—RxFIFO Underrun Condition ............................................... 288
Address = 6Bh, Rx UT Interrupt Enable/Status Register ......................................................................... 288
Bit 2—Rx FIFO Overflw Interrupt Status—RxFIFO Overrun Condition .................................................. 288
Address = 6Bh, Rx UT Interrupt Enable/Status Register ......................................................................... 289
Bit 3—RCOCA Interrupt Enable—Receive UTOPIA Change of Cell Alignment Interrupt Enable ........ 289
Bit 4—RxFIFO Underflw Interrupt Enable—Rx FIFO Underrun Condition Interrupt Enable ................ 289
Bit 5—RxFIFO Overflw Interrupt Enable—Rx FIFO Overrun Condition Interrupt Enable ..................... 289
8.0 TIMING DIAGRAMS ................................................................................................290
Ordering Information ........................................................................................................................298
Package Dimensions .........................................................................................................................299
Table of Contents ..................................................................................................................................I
List of Figures ...............................................................................................................................XVIII
List of tables ...................................................................................................................................XXII