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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
V
Bit 2—TxFEAC Enable .................................................................................................................................. 80
Bit 1—TxFEAC Go ......................................................................................................................................... 80
Bit 0—TxFEAC Busy ..................................................................................................................................... 80
Address = 1Dh, Tx DS3 FEAC Register ....................................................................................................... 80
Address = 1Eh, Tx DS3 LAPD Configuration Register ............................................................................... 81
Bit 3—Auto Retransmit ................................................................................................................................. 81
Bit 2:1 = TxLAPD Type[1, 0] .......................................................................................................................... 81
Bit 0—TxLAPD Enable .................................................................................................................................. 81
Address = 1Fh, Tx DS3 LAPD Status/Interrupt Register ............................................................................ 81
Bit 3—TxDL Start ........................................................................................................................................... 81
Bit 2—TxDL Busy .......................................................................................................................................... 82
Bit 1—TxLAPD Interrupt Enable ................................................................................................................... 82
Bit 0—TxLAPD Interrupt Status ................................................................................................................... 82
Address = 20h, PMON LCV Event Count Register—MSB .......................................................................... 82
Address = 21h, PMON LCV Event Count Register—LSB ........................................................................... 82
Address = 22h, PMON Framing Bit Error Event Count Register—MSB ................................................... 83
Address = 23h, PMON Framing Bit Error Event Count Register—LSB .................................................... 83
Address = 24h, PMON Parity Error Event Count Register—MSB ............................................................. 83
Address = 25h, PMON Parity Error Event Count Register—LSB .............................................................. 84
Address = 26h, PMON FEBE Event Count Register—MSB ....................................................................... 84
Address = 27h, PMON FEBE Event Count Register—LSB ........................................................................ 84
Address = 28h, PMON BIP-8 Error Count Register—MSB ......................................................................... 84
Address = 29h, PMON BIP-8 Error Count Register—LSB .......................................................................... 85
Address = 2Ah, PMON PLCP Framing Byte Error Count Register—MSB ................................................ 85
Address = 2Bh, PMON PLCP Framing Byte Error Count Register—LSB ................................................. 85
Address = 2Ch, PMON PLCP FEBE Count Register—MSB ....................................................................... 86
Address = 2Dh, PMON PLCP FEBE Count Register—LSB ........................................................................ 86
Address = 2Eh, PMON Received Single HEC Error Count—MSB ............................................................. 86
Address = 2Fh, PMON Received Single HEC Error Count—LSB .............................................................. 86
Address = 30h, PMON Received Multiple-Bit HEC Error—MSB ................................................................ 87
Address = 31h, PMON Received Multiple-Bit HEC Error—LSB ................................................................. 87
Address = 32h, PMON Received Idle Cell Count—MSB ............................................................................. 87
Address = 33h, PMON Received Idle Cell Count—LSB ............................................................................. 88
Address = 34h, PMON Received Valid Cell Count—MSB .......................................................................... 88
Address = 35h, PMON Received Valid Cell Count—LSB ........................................................................... 88
Address = 36h, PMON Discarded Cell Count—MSB .................................................................................. 88
Address = 37h, PMON Discarded Cell Count—LSB ................................................................................... 89
Address = 38h, PMON Transmitted Idle Cell Count—MSB ........................................................................ 89
Address = 39h, PMON Transmitted Idle Cell Count—LSB ......................................................................... 89
Address = 3Ah, PMON Transmitted Valid Cell Count—MSB ..................................................................... 90
Address = 3Bh, PMON Transmitted Valid Cell Count—LSB ...................................................................... 90
Address = 3Ch, PMON Holding Register ..................................................................................................... 90
Address = 3Dh, One Second Error Status Register ................................................................................... 90
Bit 1—Errored Second .................................................................................................................................. 91