
á
PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
139
5.0 LINE INTERFACE DRIVE
AND SCAN SECTION
The “Line Interface Drive and Scan” Section, of the
XRT7245 DS3 UNI consists of 5 output pins, three
input pins, a “Read/Write” register, and a “Read Only”
register.
The purpose of the “Line Interface Drive and Scan”
section, is to allow the user to monitor and exercise
control over many aspects of the XRT7300 DS3/E3
LIU IC without having to develop the necessary “off-
chip” glue logic.
Figure 30 presents a simply circuit schematic that
depicts how the XRT7245 DS3 UNI should be inter-
faced to the XRT7300 DS3/E3 LIU IC.
As mentioned above, the Line Interface Drive and
Scan Section, consists of five output pins and three
input pins. The logic state of the output pins are con-
trolled by the contents within the “Line Interface
Drive” Register, as depicted below.
F
IGURE
30. C
IRCUIT
S
CHEMATIC
I
LLUSTRATING
HOW
THE
XRT7245 DS3 UNI
SHOULD
BE
INTERFACED
TO
THE
XRT7295/XRT7296 DS3 L
INE
I
NTERFACE
U
NIT
DEVICES
.
+5V
Rx Data[15:0]
D[15:0]
RxOOF
RxLCD
RxRED
RxAIS
A[8:0]
TxData[15:0]
TxSoC
TxEnB*
TxClk
TxPrty
RESETB*
INT*
RW
DS
AS
DTACK*
RxClk
RxPrty
RxClav
CSB*
RxEnB*
RxSOC
TTIP
TRING
RTIP
RRING
U1
XRT7300
TPDATA
37
TNDATA
38
TCLK
36
RCLK1
31
RNEG
32
RPOS
33
TTIP
41
TRNG
40
MTIP
44
MRING
43
RRNG
9
RTIP
8
DMO
4
RLOS
24
RLOL
23
LLB
14
RLB
15
TAOS
2
TxLEV
1
ENCODIS
21
REQDIS
12
T1
1:1
1
5
4
8
T2
1:1
1
5
4
8
U2
XRT7245
Tx POS
109
TxNEG
111
TxLineClk
112
DMO
6
ExtLOS
86
RLOL
8
LLOOP
28
RLOOP
26
TAOS
2
TxLEV
24
ENCODIS
22
REQB
12
Rx POS
97
RxNEG
98
RxLineClk
99
A0
A1
A2
A3
A4
A5
A6
A7
A8
48
46
45
44
43
42
41
39
37
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
27
25
23
21
19
18
17
16
14
13
11
9
5
4
3
1
RESET
INT
CS
WRB_RW
RDB_DS
ALE_AS
Rdy_Dtck
155
29
32
35
33
157
160
MOTO
7
RxLOS
RxOOF
RxLCD
RxRED
RxAIS
88
90
30
101
92
RxSOC
RxEnB
RxClk
RxPrty
RxClav
72
81
50
74
76
TxSoC
TxClk
TxPrty
124
123
151
125
126
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
RxData6
RxData7
RxData8
RxData9
RxData10
RxData11
RxData12
RxData13
RxData14
70
68
64
62
60
58
56
54
69
67
65
63
61
57
55
53
TxData0
TxData5
TxData6
TxData7
TxData8
TxData9
TxData10
TxData11
TxData12
TxData13
TxData14
TxData15
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
R1
1
36
2
R4
270
1
2
R2
1
36
2
R3
270
1
2
R5
37.5
1
2
R6
37.5
1
2
C1
0.01uF
1
2
Line Interface Drive Register (Address = 72h)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
REQB
TAOS
Encodis
TxLev
RLOOP
LLOOP
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
0
0
0