
á
PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
87
This “Reset-upon-Read” register, along with the
“PMON Received Single HEC Error Count—MSB”
register (Address = 2Eh) contains a 16 bit represen-
tation of the number of “Single bit HEC Errors” that
have been detected by the Receive Cell Processor,
since the last read of these registers. This register
contains the LSB (or Lower byte) value of this 16-bit
expression.
3.3.2.48
PMON Received Multiple-Bit HEC Error—MSB
This “Reset-upon-Read” register, along with the
“PMON Received Multiple HEC Error Count—LSB”
register (Address = 31h) contains a 16 bit represen-
tation of the number of “Multiple-bit HEC Errors” that
have been detected by the Receive Cell Processor,
since the last read of these registers. This register
contains the MSB (or Upper byte) value of this 16-bit
expression.
3.3.2.49
PMON Received Multiple-Bit HEC Error—LSB
This “Reset-upon-Read” register, along with the
“PMON Received Multiple HEC Error Count—MSB”
register (Address = 30h) contains a 16 bit represen-
tation of the number of “Multiple-bit HEC Errors” that
have been detected by the Receive Cell Processor,
since the last read of these registers. This register
contains the LSB (or Lower byte) value of this 16-bit
expression.
3.3.2.50
PMON Received Idle Cell Count—MSB
This “Reset-upon-Read” register, along with the “PMON
Received Idle Cell Count—LSB” register (Address =
33h) contains a 16 bit representation of the number of
“Idle Cells” that have been detected by the Receive Cell
Processor, since the last read of these register. This
register contains the MSB (or Upper Byte) value of this
16-bit expression.
Address = 30h, PMON Received Multiple-Bit HEC Error—MSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
M-HEC Error Count—High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Address = 31h, PMON Received Multiple-Bit HEC Error—LSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
M-HEC Error Count—Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Address = 32h, PMON Received Idle Cell Count—MSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Rx Idle Cell Count—High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0