
XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
242
boundaries of the PLCP frames by first searching for
the Frame Alignment bytes: A1 and A2. The value of
the A1 and A2 bytes are F6h and 28h, respectively.
After the Receive PLCP Processor locates the Frame
Alignment bytes, it will then begin to read and align
itself in accordance with the POI (Path Overhead
Indicator) bytes.
The Receive PLCP processor will declare itself “in-
frame” if two consecutive sets of A1, A2 and POI bytes
are correct and if the received POIs are in the correct
sequence.
7.2.2.1.2
When the Receive PLCP Processor is operating in
the “In-Frame” mode, it means that it is continually
correctly locating the boundaries of the incoming
PLCP frames. This also enables the Receive PLCP
Processor to perform its tasks of POH byte extraction
and processing. The Receive PLCP processor will in-
dicate its detection of a PLCP frame boundary by
pulsing the RxPFrame output pin “high” at the end of
each frame. Therefore, the pulse rate of this output
In-Frame (Frame Maintenance Mode)
pin is nominally 8 kHz. The Receive PLCP Processor
will notify the localμC/μP of its transition from the
“Un-framed” to the “In-frame” state by:
Negating both the RxPOOF and RxPLOF output
pins
Negating both the POOF Status and PLOF
Status bits in the Rx PLCP Configuration/Status
Register.
Generating a “Change of OOF/LOF” status
interrupt request to the local μC/μP
1.
2.
3.
Additionally, while the Receive PLCP Processor is
operating in the “In-frame” mode, it also will be per-
forming “Frame Maintenance” functions by continually
checking for and report framing errors. The user can
monitor the number of Framing Errors that have been
detected by the Receive PLCP Processor by reading
the PMON PLCP Framing Byte Error Count Registers
which are located at Addresses 2Ah and 2Bh. The
bit-formats of these two registers are presented below.
The contents of these registers reflect the total num-
ber of PLCP Framing Errors that have been detected
since the last read of these registers. These registers
are reset upon read.
7.2.2.1.3
The Receive PLCP Processor will declare an “Out-of-
Frame” (OOF) condition, if:
Errors are detected in two consecutive framing
bytes (A1, A2), or
Two consecutive POIs values are both incorrect.
Out-of-Frame (OOF) Mode
Once the Receive PLCP Processor declares “OOF”,
then it will enter the “Out-of-Frame” state (per Figure 74).
Please note that this mode should not be confused
with the “Un-Framed” mode.
When the Receive PLCP Processor is operating in
the “OOF” mode, it will attempt to re-acquire the
“In-frame” status. However, the Receive PLCP
Processor will continue to use the previous frame
synchronization, while operating in this mode. If the
Receive PLCP Processor cannot re-acquire the
“In-Frame” status after being in the “OOF” mode for
1ms (approximately 8 PLCP frames) or more, then
the Receive PLCP Processor will declare a “Loss of
Frame” and will transition back to the “Un-Framed
Mode”.
Address = 2Ah, PMON PLCP Framing Byte Error Count Register—MSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
FA Error Count—High Byte
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
Address = 2Bh, PMON PLCP Framing Byte Error Count Register—LSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
FA Error Count—Low Byte
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0