á
PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
85
This “Reset-upon-Read” register, along with the
“PMON BIP-8 Error Count Register—LSB” (Address =
28h) contains a 16-bit representation of the total
number of BIP-8 Errors (in the incoming B1 byte) that
have been detected by the Receive PLCP Processor,
since the last read of these registers. This register
contains the MSB (or Upper Byte) value of this 16 bit
expression.
3.3.2.41
PMON BIP-8 Error Count Register—LSB
This “Reset-upon-Read” register, along with the
“PMON BIP-8 Error Count Register—MSB” (Address
= 27h) contains a 16-bit representation of the total
number of BIP-8 Errors (in the incoming B1 byte) that
have been detected by the Receive PLCP Processor,
since the last read of these registers. This register
contains the LSB (or Lower Byte) value of this 16 bit
expression.
3.3.2.42
PMON PLCP Framing Byte Error Count Register—MSB
This “Reset-upon-Read” register, along with the “PMON
Framing Byte Error Count Register—LSB” (Address =
2Bh) contains a 16-bit representation of the total
number of Framing Byte Errors (in the incoming A1
and A2 bytes) that have been detected by the Re-
ceive PLCP Processor, since the last read of these
registers. This register contains the MSB (or Upper
Byte) value of this 16 bit expression.
3.3.2.43
PMON PLCP Framing Byte Error Count Register—LSB
This “Reset-upon-Read” register, along with the “PMON
Framing Byte Error Count Register—MSB” (Address =
2Ah) contains a 16-bit representation of the total
number of Framing Byte Errors (in the incoming A1
and A2 bytes) that have been detected by the Re-
ceive PLCP Processor, since the last read of these
registers. This register contains the LSB (or Lower
Byte) value of this 16 bit expression.
Address = 29h, PMON BIP-8 Error Count Register—LSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
BIP-8 Error Count—Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Address = 2Ah, PMON PLCP Framing Byte Error Count Register—MSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
FA Error Count—High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Address = 2Bh, PMON PLCP Framing Byte Error Count Register—LSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
FA Error Count—Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0