XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
42
2.
The μC/μP can read in the contents of a given
Performance Monitor (PMON) register in a single
read cycle.
As a consequence, the PMON Holding Register is
not needed in the “16-bit” mode.
All “Read” and “Write” operations are aligned to
“even-numbered” addresses, within the UNI
Address Space.
As a consequence, the least significant address bus
pin, A0 is ignored, whenever the UNI is operating in
the “16-bit” Mode.
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3.2.2
As mentioned earlier, the Microprocessor Interface
block supports data transfer between the UNI and the
μC/μP (e.g., “Read” and “Write” operations) via two
modes: the “Programmed I/O” and the “Burst”
Modes. Each of these “Data Access” Modes are dis-
cussed in detail below.
Data Access Modes
3.2.2.1
“Programmed I/O” is the conventional manner in
which a microprocessor exchanges data with a pe-
ripheral device. However, it is also the slowest meth-
od of data exchange between the UNI and the μC/
μP; as will be described in this text.
The next two sections present detailed information
on Programmed I/O Access, when the XRT7245 DS3
UNI is operating in the “Intel Mode” and in the “Motor-
ola Mode”.
Data Access using Programmed I/O
3.2.2.1.1
Programmed I/O Access in the
“Intel” Mode
If the XRT7245 DS3 UNI is interfaced to an “Intel-
type” μC/μP (e.g., the 80x86 family, etc.), then it
should be configured to operate in the “Intel” mode
(by tying the “MOTO” pin to ground). Intel-type
“Read” and “Write” operations are described below.
3.2.2.1.1.1
Whenever an Intel-type μC/μP wishes to read the con-
tents of a register or some location within the Receive
LAPD Message buffer or the Receive OAM Cell Buffer,
(within the UNI device), it should do the following.
Place the address of the “target” register or
buffer location (within the UNI) on the Address
Bus input pins A[8:0].
The Intel Mode Read Cycle
1.
2.
While the μC/μP is placing this address value on
the Address Bus, the Address Decoding circuitry
(within the user’s system) should assert the CS*
(Chip Select) pin of the UNI, by toggling it “l(fā)ow”.
This action enables further communcation
between the μC/μP and the UNI Microprocessor
Interface block.
Toggle the ALE_AS (Address Latch Enable)
input pin “high”. This step enables the “Address
Bus” input drivers, within the Microprocessor
Interface block of the UNI.
After allowing the data on the Address Bus pins
to settle (by waiting the appropriate “Address”
Data Setup time”), the μC/μP should toggle the
ALE_AS pin “l(fā)ow”. This step causes the UNI
device to “l(fā)atch” the contents of the “Address
Bus” into its internal circuitry. At this point, the
address of the register or buffer locations (within
the UNI), has now been selected.
Next, the μC/μP should indicates that this current
bus cycle is a “Read” Operation by toggling the
RdB_DS (Read Strobe) input pin “l(fā)ow”. This
action also enables the bi-directional data bus
output drivers of the UNI device. At this point, the
“bi-directional” data bus output drivers will pro-
ceed to drive the contents of the “l(fā)atched
addressed” register (or buffer location) onto the
bi-directional data bus, D[15:0].
Immediately after the μC/μP toggles the “Read
Strobe” signal “l(fā)ow”, the UNI device will toggle
the Rdy_Dtck output pin “l(fā)ow”. The UNI device
does this in order to inform the μC/μP that the
data (to be read from the data bus) is “NOT
READY” to be “l(fā)atched” into the μC/μP
After some settling time, the data on the “bi-
directional” data bus will stabilize and can be
read by the μC/μP The XRT7245 DS3 UNI will
indicate that this data can be read by toggling the
Rdy_Dtck (READY) signal “high”.
After the μC/μP detects the Rdy_Dtck signal
(from the XRT7245 DS3 UNI), it can then termi-
nate the Read Cycle by toggling the RdB_DS
(Read Strobe) input pin “high”.
Figure 8 presents a timing diagram which illustrates
the behavior of the Microprocessor Interface signals,
during an “Intel-type” Programmed I/O Read Operation.
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