
á
PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
257
If the user writes a “0” to this bit-field, then the Idle
Cells will be retained and will ultimately be sent on to
the User Cell Filter within the Receive Cell Processor
block. However, if the user writes a “1” to this bit-field,
then the Receive Cell Processor will discard all detect-
ed Idle-cells.
If the user wishes to have the Receive Cell Processor
discard the Idle Cells then he/she must specify the
header byte patterns of these Idle cells. The Idle Cell
header byte pattern is defined based upon the content
of 8 read/write registers. These eight registers are the
four “Rx CP Idle Cell Pattern Header byte registers,
and the four “Rx CP Idle Cell Mask Header—Byte”
Registers. In short, when a cell reaches the “Idle Cell
Filter” portion of the Receive Cell Processor, the
contents of each header byte of this cell (bytes 1
through 4), will be compared against the contents of
the corresponding “Rx CP Idle Cell Pattern Header
Byte” registers; based upon constraints specified by
the contents within the “Rx CP Idle Cell Mask Header
Byte” registers. The use of these registers in “Idle
Cell Identification” and filtering is illustrated in the
example below.
Example—Idle Cell Filtering
For example, header byte 1 of a given incoming cell
(which may be an Idle cell or a User cell) will be sub-
jected to a bit-by-bit comparison to the contents of
the “Rx CP Idle Cell Pattern Header Byte-1” register
(Address = 50h). The purpose of having the Receive
Cell Processor perform this comparison is to deter-
mine if this incoming cell is an Idle Cell or not. The
contents of the “Rx CP Idle Cell Mask Header Byte-1”
register (Address = 54h) also plays a role in this com-
parison process. For instance, if bit-field “0” within the
“Rx CP Idle Cell Mask Header Byte-1” register
contains a “1”, then the Receive Cell Processor will
perform the comparison operation between bit-field
“0” within the “Rx CP Idle Cell Pattern Header Byte-1”
register; and bit-field “0” within header byte 1 of the
newly received cell. Conversely, if bit-field “0” within
the “Rx CP Idle Cell Mask Header Byte-1” register
contains a “0”, then this comparison will not be made
and bit-field “0” will be treated as a “don’t care”. The
role of these two read/write registers, in these compar-
ison operations is more clearly defined in Table 57,
below.
RxCP Configuration Register (Address = 4Ch)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
RxLCD
RDPChk
Pattern
RDPChk
Pattern Enable
Idle Cell
Discard
OAM Check
Bit
De-Scramble
Enable
RxCoset
Enable
HEC Error
Ignore
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
x
x
x
x
x
x
x
T
ABLE
57: I
LLUSTRATION
OF
THE
R
OLE
OF
THE
“R
X
CP I
DLE
C
ELL
P
ATTERN
H
EADER
B
YTE
” R
EGISTER
,
AND
THE
“R
X
CP I
DLE
C
ELL
M
ASK
H
EADER
B
YTE
” R
EGISTER
Content of Header Byte-1 (of Incoming Cell)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
1
0
1
0
0
1
0
1
Content of “Rx CP Idle Cell Mask Header Byte-1 Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
1
1
1
1
0
0
0
0
Content of “Rx CP Idle Cell Header Byte-1 Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
1
0
1
0
1
1
0
1