
XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
142
5.1
Bit-Fields within the Line Interface Scan
Register
The meaning/role of each of these bit-field and their
corresponding input pins are defined below.
Bit 2—DMO (Drive Monitor Output)
This “Read-Only” bit-field indicates the logic state of
the DMO input pin of the UNI device. This input pin is
intended to be connected to the DMO output pin of
the XRT7300 DS3/E3/STS-1 LIU IC. If this bit-field
contains a logic “1”, then the “DMO” input pin is
“high”. The XRT7300 DS3/E3/STS-1 LIU IC will set
this pin “high” if the drive monitor circuitry (within the
XRT7300 device) has not detected any bipolar signals
at the MTIP and MRING inputs (of the XRT7300
device) within the last 128 ± 32 bit periods.
Conversely, if this bit-field contains a logic “0”, then
the “DMO” input pin is “high”. The XRT7300 DS3/E3/
STS-1 LIU IC will set this pin “l(fā)ow” if bipolar signals are
being detected at the “MTIP” and “MRING” input pins.
For more information on the use/purpose of the Drive
Monitor feature, within the XRT7300 LIU IC, please
see the “XRT7300 DS3/E3/STS-1 LIU IC” Data Sheet.
Note:
If this customer is not using the XRT7300 DS3/E3/
STS-1 LIU IC, then he/she can use this register bit-field
and input pin for a variety of other purposes.
Bit 1—RLOL (Receive Loss of Lock)
This “Read-Only” bit-field indicates the logic state of
the “RLOL” input pin of the UNI device. This input pin
is intended to be connected to the “RLOL” output pin
of the XRT7300 DS3/E3/STS-1 LIU IC. If this bit-field
contains a logic “1”, then the RLOL input pin is “high”.
The XRT7300 LIU IC will set this pin “high” if the
clock recovery phase-locked-loop circuitry (within the
XRT7300 device) has lost “l(fā)ock” with the incoming
DS3 data-stream and is not properly recovering clock
and data.
Conversely, if this bit-field contains a logic “0”, then
the RLOL input pin is “l(fā)ow”. The XRT7300 DS3/E3/
STS-1 LIU IC will hold this pin “l(fā)ow” as long as this
“clock recovery phase-locked-loop” circuitry (within
the XRT7300 device) is properly “l(fā)ocked” onto the
incoming DS3 data-stream, and is properly recovering
clock and data from this data-stream.
For more information on the “Loss of Lock” Declaration
criteria (within the XRT7300 device), please consult
the “XRT7300 DS3/E3/STS-1 LIU IC” data sheet.
Note:
If the customer is not using the XRT7300 DS3/E3/
STS-1 LIU IC, then he/she can use this bit-field, and the
“RLOL” input pin for other purposes.
Bit 0—RLOS (Receive Loss of Signal)
This “Read-Only” bit-field indicates the logic state of
the “RLOS” input pin of the UNI device. This input pin
is intended to be connected to the “RLOS” output pin
of the XRT7300 DS3/E3/STS-1 LIU IC. If this bit-field
contains a logic “1”, then the RLOS input pin is “high”.
The XRT7300 LIU IC will drive this signal “high” if it is
currently declaring an “LOS” (Loss of Signal) condition.
Conversely, if this bit-field contains a logic “0”, then
the “RLOS” input pin is “l(fā)ow”. The XRT7300 LIU IC
will drive this signal “l(fā)ow”, if it is NOT currently declar-
ing an “LOS” (Loss of Signal) condition.
For more information on the “LOS Declaration/Clear-
ance” criteria, used by the XRT7300 device, please
see the “XRT7300 DS3/E3/STS-1 LIU IC” Data Sheet.
Note:
Asserting the “RLOS” input pin will cause the UNI
device to generate a “Change in LOS Condition” Interrupt
and declare an LOS (Loss of Signal) condition to the Micro-
processor/Microcontroller. Therefore, the user is advised
not to use the “RLOS” input pin as a general-purpose
input pin.
Address = 73h, Line Interface Scan Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
DMO
RLOL
RLOS
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0