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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
227
7.1.2.3.3
The Receive DS3 Framer will identify and declare an
“Idle Condition” if it receives a sufficient number of
M-Frames that meets all of the following conditions.
Valid M-bits, F-bits, and P-bits
The 3 CP-bits (in F-Frame #3) are zeros.
The X-bits are set to “1”
The payload portion of the DS3 Frame exhibits a
repeating “1100...” pattern.
Idle (Condition) Alarm
The Receive DS3 Framer circuitry includes an Up/
Down Counter that is used to track the number of
M-frames that are detected as exhibiting the “Idle
Condition” by the Receive DS3 Framer. The contents
of this counter is set to zero upon reset or power up.
This counter is then incremented whenever the
Receive DS3 Framer detects an “Idle-type” M-frame.
The counter is decremented, or kept at zero if a “non-
Idle” M-frame is detected. If the Receive DS3 Framer
detects a sufficient number of “Idle-type” M-frames,
such that the counter reaches the number “63”, then
the Receive DS3 Framer will declare the “Idle Condi-
tion”. Explained another way, the Receive DS3 Framer
will declare an “Idle Condition” if the number of “Idle-
Pattern” M-frames is detected such that it meets the
following conditions.
N
IDLE
- N
VALID
63,
where: N
IDLE
= the number of M-frames containing
“Idle Patterns”
N
VALID
= the number of M-frames not exhibiting the
“Idle Pattern”
Any time the contents of this “Up/Down” Counter
reaches the number 63, then the Receive DS3
Framer will:
Set Bit 5 of the Rx DS3 Configuration and Status
Register, as depicted below.
Generate a “Change in Idle Status” Interrupt
Request to the local μP/μC.
The Receive DS3 Framer will negate the “Idle Condi-
tion” if it has detected a sufficient number of “Non-Idle”
M-frames, such that this Up/Down Counter reaches
the value “0”.
7.1.2.3.4
Detection of (FERF) Yellow Alarm
Condition
The Receive DS3 Framer will identify and declare a
“Yellow Alarm” condition or a “Far-End Receive Failure”
(FERF) condition, if it starts to receive DS3 frames
with all of its X-bits set to “0”.
When the Receive DS3 Framer detects a “Yellow
Alarm” condition in the incoming DS3 frames, then it
will then do the following.
It will assert the “RxFERF” (bit-field 4) within the Rx
DS3 Status Register, as depicted below.
This bit-field will remain asserted for the duration that
the “Yellow Alarm” condition exists.
The Receive DS3 Framer will also generate a
“Change in FERF Status” interrupt to the local
μ
P/
μ
C.
Consequently, the Receive DS3 Framer will also
assert the “FERF Interrupt Status” bit, within the Rx
DS3 Interrupt Status Register, as depicted below.
Rx DS3 Configuration and Status Register, (Address = 0Eh)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Rx AIS
Rx LOS
Rx Idle
Rx OOF
Int LOS Disable
Framing on Parity
F-Sync Algo
M-Sync Algo
X
X
1
X
X
X
X
X
Address = 0Fh, Rx DS3 Status Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
RxFERF
RxAIC
RxFEBE [2]
RxFEBE [1]
RxFEBE [0]
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
1
x
x
x
x