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參數(shù)資料
| 型號(hào)： | XRT7245 |
| 廠商： | Exar Corporation |
| 英文描述： | DS3 ATM User Network Interface(DS3異步傳輸模式用戶網(wǎng)絡(luò)接口) |
| 中文描述： | DS3自動(dòng)柜員機(jī)用戶網(wǎng)絡(luò)接口（DS3異步傳輸模式用戶網(wǎng)絡(luò)接口） |
| 文件頁(yè)數(shù)： | 41/324頁(yè) |
| 文件大?。?/td> | 4103K |
| 代理商： | XRT7245 |
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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
41
3.2.1.1
Interfacing the UNI to the μC/μP Over
an 8-Bit Wide Bi-Directional Data Bus.
In general, interfacing the UNI to an “8-bit” μC/μP is
quite straight-forward. This is because most of the
registers, within the UNI, are 8-bits wide. Further, in
this mode, the μC/μP can read or write data into both
even and odd numbered addresses within the UNI
address space.
Reading Performance Monitor (PMON) Registers
The only awkward issue that the user should be wary
of (while operating in the “8-bit” mode) occurs when-
ever the μC/μP needs to read the contents of one of
the PMON (Performance Monitor) registers.
The XRT7245 DS3 UNI Device consists of the following
PMON Registers.
PMON LCV Event Count Register
PMON Framing Error Event Count Register
PMON Received FEBE Event Count Register
PMON Parity Error Event Count Register
PMON Received Single-Bit HEC Error Count
Register
PMON Received Multiple-Bit HEC Error Count
Register
PMON Received Idle Cell Count Register
PMON Received Valid Cell Count Register
PMON Discarded Cell Count Register
PMON Transmitted Idle Cell Count Register
PMON Transmitted Valid Cell Count Register.
Unlike most of the registers within the UNI, the
PMON registers are “16-bit” registers (or 16-bits
wide). Table 4, lists each of these PMON registers as
consisting of two 8-bit registers. One of these “8-bit”
register is labeled “MSB” (or Most Significant Byte”)
and the other register is labeled “LSB” (or Least
Significant Byte). When an “8-bit” PMON Register is
concatenated with its “companion 8-bit” PMON Reg-
ister, one obtains the “full 16-bit expression” within
that PMON Register.
The consequence of having these 16-bit registers is
that an “8-bit” μC/μP will have to perform two consec-
utive read operations in order to read in the full 16-bit
expression contained within a given PMON register.
To complicate matters, these PMON Registers are
“Reset-Upon-Read” registers. More specifically,
these PMON Register are “Reset-Upon-Read” in the
sense that, the entire “16-bit” contents, within a given
PMON Register is reset, as soon as an “8-bit” μC/μP
reads in either “byte” of this “two-byte” (e.g., 16 bit)
expression.
For Example
Consider that an “8-bit” μC/μP needs to read in the
“PMON LCV Event Count” Register. In order to ac-
complish this task, the 8-bit μC/μP is going to have to
read in the contents of “PMON LCV Event Count
Register—MSB” (located at Address = 0x40) and the
contents of the “PMON LCV Event Count Register—
LSB (located at Address = 0x41). These two “eight-
bit” registers, when concatenated together, make up
the “PMON LCV Event Count” Register.
If the 8-bit μC/μP reads in the “PMON LCV Event
Count—LSB” register first; then the entire “PMON
LCV Event Count” register will be reset to 0x0000. As
a consequence, if the 8-bit μC/μP attempts to read in
the “PMON LCV Event Count-MSB” register in the
very next read cycle, it will read in the value 0x00.
The PMON Holding Register
In order to “get-around” this “Reset-Upon-Read”
problem, the XRT7245 DS3 UNI device includes a
special register, which permits “8-bit” μC/μP to read
in the full 16-bit contents of these PMON registers.
This special register is called the “PMON Holding”
Register; and is located at 0x56 within the UNI Ad-
dress space.
The way the PMON Holding register works is as fol-
lows. Whenever an “8-bit” μC/μP reads in one of the
bytes (of the “2-byte” PMON register); the contents of
the “unread” (e.g., other) byte will be stored in the
PMON Holding Register. Therefore, the “8-bit” μC/μP
must then read in the contents of the PMON Holding
Register in the very next read operation.
In Summary: Whenever an “8-bit” μC/μP needs to
read a PMON Register, it must execute the follow-
ing steps.
Step 1:
Read in the contents of a given “8-bit” PMON
Register (it does not matter whether the μC/μP reads
in the “-MSB” or the “-LSB” register).
Step 2:
Read in the contents of the “PMON Holding”
Register (located at Address = 0x56). This register
will contain the contents of the “other” byte.
3.2.1.2
Interfacing the UNI to the μC/μP Over a
16-Bit Wide Bi-Directional Data Bus
Whenever the XRT7245 DS3 UNI is interfaced to a
μC/μP over a 16-bit wide bi-directional data, then the
following statements are true.
Each read and write operation will be accessing
two “Configuration Registers” at once.
1.
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