á
PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
23
126
TxClav
O
Transmit UTOPIA Interface—Cell Available Output Pin:
This output pin supports
data flow control between the ATM Layer processor and the Transmit UTOPIA Inter-
face block. The exact functionality of this pin depends upon whether the UNI is operat-
ing in the “Octet Level” or “Cell Level” handshaking mode.
Octet Level Handshaking:
When the Transmit UTOPIA Interface block is operating in
the octet-level handshaking mode, this signal is negated (toggles “l(fā)ow”) when the
TxFIFO is not capable of handling four more write operations; by the ATM Layer pro-
cessor to the Transmit UTOPIA Interface block. This signal will be asserted when the
TxFIFO is capable of receiving four or more write operations of ATM cell data.
Cell Level Handshaking:
When the Transmit UTOPIA Interface block is operating the
cell-level handshaking mode, this signal is asserted (toggles “high”) when the TxFIFO
is capable of receiving at least one more full cell of data from the ATM Layer proces-
sor. This signal is negated, if the TxFIFO is not capable of receiving one more full cell
of data from the ATM Layer processor.
Multi-PHY Operation:
When the UNI chip is operating in the Multi-PHY mode, this
signal will be tri-stated until the TxClk cycle following the assertion of a valid address
on the Transmit UTOPIA Address bus input pins (e.g., when the contents on the Trans-
mit UTOPIA Address bus pins match that within the Transmit UTOPIA Address Regis-
ter). Afterwards, this output pin will behave in accordance with the cell-level
handshake mode.
127
GND
***
Ground Signal Pin.
128
TxData8
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
129
TxData0
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
130
TxData9
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
131
TxData1
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
132
TxData10
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
133
TxData2
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
134
TxData11
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
135
TxData3
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
136
VDD
***
Power Supply Pin
137
TxData4
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
138
TxData12
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
139
TxData5
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
140
TxData13
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
141
TxData6
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
142
TxData14
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
143
TxData7
I
Transmit UTOPIA Data Bus Input:
Please see description for TxData15
144
TxData15
I
Transmit UTOPIA Data Bus Input—MSB:
This input pin, along with TxData14
through TxData0 comprise the Transmit UTOPIA Data Bus input pins. When the ATM
Layer Processor wishes to transmit ATM cell data through the XRT7245 DS3 UNI, it
must place this data on these pins. The data, on the Transmit UTOPIA Data Bus is
latched into the Transmit UTOPIA Interface block on the rising edge of TxClk.
145
VDD
***
Power Supply Pin
PIN DESCRIPTION (CONT’D)
P
IN
N
O
.
S
YMBOL
T
YPE
D
ESCRIPTION