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參數(shù)資料
| 型號(hào)： | XRT7245 |
| 廠商： | Exar Corporation |
| 英文描述： | DS3 ATM User Network Interface(DS3異步傳輸模式用戶(hù)網(wǎng)絡(luò)接口) |
| 中文描述： | DS3自動(dòng)柜員機(jī)用戶(hù)網(wǎng)絡(luò)接口（DS3異步傳輸模式用戶(hù)網(wǎng)絡(luò)接口） |
| 文件頁(yè)數(shù)： | 119/324頁(yè) |
| 文件大?。?/td> | 4103K |
| 代理商： | XRT7245 |
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á
PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
119
an inconvenience. However, all of the PMON registers
within the UNI IC contain 16 bits. Consequently, any
reads of the PMON registers will require two read
cycles.
The XRT7245 DS3 UNI includes a feature that will
make reading a PMON register a slightly less compli-
cated task. The UNI chip address space contains a
register known as the “PMON Holding” register, which
is located at 3Ch. Whenever the local μP (while oper-
ating over an 8-bit data bus with the Microprocessor
Interface of the UNI) reads in an 8-bit value of a given
PMON register (e.g., either the upper-byte or the lower
byte value of the PMON register); the other 8-bit value
of that PMON register will automatically be accessible
by reading the PMON Holding register.
Hence, whenever the Microprocessor Interface is con-
figured to operate over an 8-bit data bus, anytime the
local
μ
P is trying to read in the contents of a PMON
register, the first read access must be made directly to
one of the 8-bit values of the PMON registers (e.g.,
for example: the PMON Received Single-Bit HEC
Error Count—MSB, Address = 2Eh). However, the
second read can always be made to a constant location
in system memory; the PMON Holding Register.
3.6
The Interrupt Structure within the UNI
Microprocessor Interface Section
The XRT7245 UNI device is equipped with a sophisti-
cated Interrupt Servicing Structure. This Interrupt
Structure includes an Interrupt Request output, INT*,
numerous Interrupt Enable Registers and numerous
Interrupt Status Registers. The Interrupt Servicing
Structure, within the UNI contains two levels of hier-
archy. The top level is at the functional block level
(e.g, the Receive DS3 Framer, Transmit DS3 Framer,
Receive PLCP Processor, etc.) The lower hierarchical
level is at the individual interrupt or “source” level.
Each hierarchical level consists of a complete set of
Interrupt Status Registers/bits and Interrupt Enable
Registers/bits, as will be discussed below.
Most of the functional blocks, within the UNI, are
capable of generating Interrupt Requests to the local
μC/μP The UNI device Interrupt Structure has been
carefully designed to allow the user to quickly deter-
mine the exact source of the interrupt (with minimal
latency) which will aid the local μP/μC in determining
which interrupt service routine to call up in order to
eliminate the condition(s) causing the interrupt.
Table 5 lists all of the possible conditions that can
generate interrupts, within each functional block of
the UNI.
T
ABLE
5: L
IST
OF
ALL
OF
THE
P
OSSIBLE
C
ONDITIONS
THAT
CAN
G
ENERATE
I
NTERRUPTS
WITHIN
THE
XRT7245 UNI D
EVICE
F
UNCTIONAL
B
LOCK
I
NTERRUPTING
C
ONDITION
Transmit UTOPIA Interface Block
Detection of Parity Errors
Change of Cell Alignment
Tx FIFO Overrun
Transmit Cell Processor
Data path integrity error occurrence
Transmit PLCP Processor
None
Transmit DS3 Framer
FEAC Message Transfer Complete
LAPD Message frame Transfer Complete
Receive DS3 Framer
Change of State on Receive LOS, OOF, AIS, Idle Detection
Validation and removal of received FEAC Code
New PMDL Message in Rx LAPD Message Buffer
Parity Errors
Receive PLCP Processor
Change of OOF State
Change of LOF State
Receive Cell Processor
HEC Errors
OAM Cell Received
Loss of Cell Delineation
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