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參數(shù)資料
| 型號(hào)： | XRT7245 |
| 廠商： | Exar Corporation |
| 英文描述： | DS3 ATM User Network Interface(DS3異步傳輸模式用戶(hù)網(wǎng)絡(luò)接口) |
| 中文描述： | DS3自動(dòng)柜員機(jī)用戶(hù)網(wǎng)絡(luò)接口（DS3異步傳輸模式用戶(hù)網(wǎng)絡(luò)接口） |
| 文件頁(yè)數(shù)： | 284/324頁(yè) |
| 文件大小： | 4103K |
| 代理商： | XRT7245 |
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XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
284
Recall, that the Receive UTOPIA Interface blocks were
assigned these addresses by writing these values into
the “Rx UTOPIA Address Register” (Address = 6Ch)
within their “host” UNI device. The discussion of the
Transmit UTOPIA Interface blocks, within UNIs #1
and #2 is presented in Section 6.1.2.3.2.1.
Polling Operation
Consider that the ATM Layer processor is currently
reading a continuous stream of cells from UNI #1.
While reading this cell data from UNI #1, the ATM
Layer processor can also “poll” UNI #2 for “availability”
(e.g., tries to determine if the RxFIFO within UNI #2,
contains some ATM cell data that needs to be read).
The ATM Layer Processor’s Role in the “Polling”
Operation
The ATM Layer processor accomplishes this “polling”
operation by executing the following steps.
Assert the RxEnB* input pin (if it not asserted
already).
The UNI device (being “polled”) will know that this is
only a “polling” operation, if the RxEnB* input pin is
asserted, prior to detecting its UTOPIA Address on
the “UTOPIA Address” bus.
The ATM Layer processor places the address of
the Receive UTOPIA Interface Block of UNI #2
onto the UTOPIA Address Bus, Ut_Addr[4:0],
The ATM Layer processor will then check the
value of its “RxClav_in” input pin (see Figure 91).
1.
2.
3.
The UNI Device’s Role in the “Polling” Operation
UNI #2 will sample the signal levels placed on its
Rx UTOPIA Address input pins (RxAddr[4:0]) on the
rising edge of its “Receive UTOPIA Interface block”
clock input signal, RxClk. Afterwards, UNI #2 will com-
pare the value of these “Receive UTOPIA Address
Bus input pin” signals with that of the contents of its
“Rx UTOPIA Address Register” (Address = 6Ch).
If these values do not match (e.g., RxAddr[4:0] μ 03h)
then UNI #2 will keep its “RxClav” output signal “tri-
stated”; and will continue to sample its “Receive
UTOPIA Address bus input” pins, with each rising
edge of RxClk.
If these two values do match (e.g., RxAddr[4:0] = 03h)
then UNI #2 will drive its “RxClav” output pin to the
appropriate level, reflecting its RxFIFO “fill status”.
Since the UNI is automatically operating in the “Cell
Level Handshaking” mode, while it is operating in the
“Multi-PHY” mode, the UNI will drive the RxClav out-
put signal “high” if it contains at least one complete
cell of data that needs to be read by the ATM Layer
processor. Conversely, the UNI will drive the “RxClav”
output signal “l(fā)ow” if its RxFIFO is depleted, or does
not contain at least one full cell of data.
When UNI #2 has been selected for “polling”, UNI #1
will continue to keeps its “RxClav” output signal “tri-
stated”. Therefore, when UNI #2 is driving its “RxClav”
output pin to the appropriate level; it will be driving
the entire “RxClav” line, within the “Multi-PHY” system.
Consequently, UNI#1 will also be driving the
“RxClav_in” input pin of the ATM Layer processor
(see Figure 92).
If UNI #2 drives the “RxClav” line “l(fā)ow”, upon the
application of its address on the UTOPIA Address
bus, then the ATM Layer processor will “l(fā)earn” that
UNI #2 does not contain any ATM cell data that is
ready to be read. However, if UNI #2 drives the Rx-
Clav line “high” (during “polling”), then the ATM Layer
processor will know that UNI#2 contains at least one
cell of data that needs to be read.
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