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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
169
The user can enable or disable this modulo-2 addi-
tion, by writing the appropriate value to bit 6 (Coset
Enable) within the “TxCP Control” Register, as de-
picted below.
A “1” in this bit-field will enable this modulo addition.
Conversely, a “0” in this bit-field will disable this
operation.
Upon power up or reset, the Transmit Cell Processor
will be configured such that the coset polynomial is
modulo-2 added to the HEC byte prior to insertion in-
to the cell. The user must write a “0” to this bit in or-
der to disable this operation.
6.2.2.1.4
Inserting Errors into the HEC Byte
via Software Control
The XRT7245 DS3 UNI allows the user to insert errors
into the HEC bytes of “outbound” cells in order to
support equipment testing. One such test that the user
may wish to verify is that the HEC byte verification
(e.g., error detection and/or correction) features of
some “Far-End” terminal equipment is functioning
properly. The user would conduct this test by trans-
mitting cells with erroneous HEC byte values to the
“unit under test” (UUT). The user can exercise this
option by writing the appropriate data into the TxCP
Error Mask register, which is located at address 62h
within the UNI.
The Transmit Cell Processor automatically XORs the
HEC Byte (or each “outbound” cell) with the contents
of this register. The result of this operation is written
back into the fifth octet position of each of these cells.
Therefore, if the user does not wish to inject errors in-
to the HEC byte, he/she should insure that the con-
tents of this register is 00h, the default value.
6.2.2.2
The Cell Scrambler takes bytes 6 through 53 of each
cell (the payload) and scrambles the contents of these
The Cell Scrambler
bytes. The purpose of scrambling the cell payload
bytes is to reduce the possibility of the contents of
the cell payload mimicking patterns that are used for
framing and cell delineation purposes. The scrambler
generating polynomial is x
43
+ 1. The user can enable
or disable the Cell Scrambler by setting or clearing bit 7
(Scrambler Enable) within the “TxCP Control” Register,
as depicted below.
TxCP Control Register (Address = 60h)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Scrambler
En
Coset
Enable
HEC Insert
Enable
TDPChk
Pattern
GFC Insert
Enable
TDPErr
Interrupt
Enable
Idle Cell
HEC CalEn
TDPErr
Interrupt
Status
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RUR
TxCP Error Mask Register; (Address = 62h)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
HEC Error Mask Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TxCP Control Register (Address = 60h)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Scrambler
Enable
Coset
Enable
HEC Insert
Enable
TDPChk
Pattern
GFC Insert
Enable
TDPErr
Interrupt
Enable
Idle Cell
HEC CalEn
TDPErr
Interrupt
Status
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RUR
x
1
1
1
0
0
1
0