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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
63
3.3.2.4
Version Number Register
3.3.2.5
UNI Interrupt Enable Register
Bit 7—Rx DS3 Interrupt Enable
This “Read/Write” bit-field allows the user to globally
disable all “Receive DS3 Framer” block interrupts; or
to enable those “Receive DS3 Framer” interrupts that
are enabled via the “Rx DS3 Interrupt Status Register
(Address = 11h), the “Rx DS3 FEAC Interrupt En-
able/Status Register (Address = 13h) and the Rx
DS3 LAPD Control Register (Address = 14h).
Writing a “0” to this bit-field disables ALL “Receive
DS3 Framer” interrupts (independent of the enable/
disable status of these interrupts within these other
registers). Writing a “1” to this bit-field enables those
“Receive DS3 Framer” interrupt that have already
been enabled via these other registers.
Bit 6—Rx PLCP Interrupt Enable
This “Read/Write” bit-field allows the user to globally
disable all “Receive PLCP Processor” related inter-
rupts; or to enable those “Receive PLCP Processor”
interrupts that are enabled via the “Rx PLCP Interrupt
Enable” Register (Address = 45h).
Writing a “0” to this bit-field disables ALL “Receive
PLCP Processor” related interrupts (independent of
the enable/disable status of these interrupts via the
“Rx PLCP Interrupt Enable Register”). Writing a “1” to
this bit-field enables those “Receive PLCP Proces-
sor” related interrupts that have already been en-
abled via the “Rx PLCP Interrupt Enable Register”.
Bit 5—Rx CP Interrupt Enable
This “Read/Write” bit-field allows the user to globally
disable all “Receive Cell Processor” related inter-
rupts; or to enable those interrupts that have been
enabled via the “Rx CP Interrupt Enable” Register
(Address = 4Eh).
Writing a “0” to this bit-field disables ALL “Receive
Cell Processor” block interrupts (independent of the
enable/disable status of these interrupts via the “Rx
CP Interrupt Enable” Register). Writing a “1” to this bit-
field enables those “Receive Cell Processor block”
interrupts that have already been enabled via the “Rx
CP Interrupt Enable” Register.
Bit 4—Rx UTOPIA Interrupt Enable
This “Read/Write” bit-field allows the user to globally
disable all “Receive UTOPIA Interface block” inter-
rupts; or to enable those interrupts that have been en-
abled via the “Rx UTOPIA Interrupt Enable/Status”
Register (Address = 6Bh).
Writing a “0” to this bit-field disables ALL “Receive
UTOPIA Interface block” interrupts (independent of
the enable/disable status of these interrupts within
the “Rx UTOPIA Interrupt Enable/Status” Register).
Writing a “1” to this bit-field enables those “Receive
UTOPIA Interface block” related interrupts that have
already been enabled via the “Rx UTOPIA Interrupt
Enable/Status” register.
Address = 03h, Version Number Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Version Number
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
1
1
Address = 04h, UNI Interrupt Enable Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
RxDS3
Interrupt
Enable
RxPLCP
Interrupt
Enable
RxCP
Interrupt
Enable
Rx UTOPIA
Interrupt
Enable
Tx UTOPIA
Interrupt
Enable
Tx CP
Interrupt
Enable
Tx DS3
Interrupt
Enable
One Sec
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0