á
PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
89
This “Reset-upon-Read” register, along with the
“PMON Discarded Cell Count—LSB” register (Ad-
dress = 37h) contains a 16 bit representation of the
number of cells that have been discarded by the Re-
ceive Cell Processor, since the last read of these regis-
ters. This register contains the MSB (or Upper byte) val-
ue of this 16 bit expression.
Please note that this expression includes Idle cells,
cells with HEC byte errors, and cells filtered or re-
moved by the User Cell Filter.
3.3.2.55
PMON Discarded Cell Count—LSB
This “Reset-upon-Read” register, along with the
“PMON Discarded Cell Count—MSB” register (Ad-
dress = 36h) contains a 16 bit representation of the
number of cells that have been discarded by the Re-
ceive Cell Processor, since the last read of these regis-
ters. This register contains the LSB (or Lower byte) val-
ue of this 16 bit expression.
Please note that this expression includes Idle cells,
cells with HEC byte errors, and cells filtered or re-
moved by the User Cell Filter.
3.3.2.56
PMON Transmitted Idle Cell Count—MSB
This “Reset-upon-Read” register, along with the “PMON
Transmitted Idle Cell Count—LSB” register (Address =
39h) contains a 16-bit representation of the number
of “Idle Cells” that have been generated and transmit-
ted by the Transmit Cell Processor, since the last
read of these registers. This register contains the
MSB (or Upper byte) value of this 16 bit expression.
3.3.2.57
PMON Transmitted Idle Cell Count—LSB
This “Reset-upon-Read” register, along with the “PMON
Transmitted Idle Cell Count—MSB” register (Address =
38h) contains a 16-bit representation of the number
of “Idle Cells” that have been generated and transmit-
ted by the Transmit Cell Processor, since the last
read of these registers. This register contains the
LSB (or Lower byte) value of this 16 bit expression.
Address = 37h, PMON Discarded Cell Count—LSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Cell Drop Count—Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Address = 38h, PMON Transmitted Idle Cell Count—MSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Tx Idle Cell Count—High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Address = 39h, PMON Transmitted Idle Cell Count—LSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Tx Idle Cell Count—Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0