XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
72
3.3.2.17
Rx DS3 Interrupt Status Register
Bit 7—CP Bit Error Interrupt Status
This “Reset Upon Read” bit-field indicates whether
or not the “Detection of CP-Bit Error” interrupt has
occurred since the last read of this register. This bit-
field will be ‘0’ if the “Detection of CP-Bit Error”
interrupt has NOT occurred since the last read of this
register. This bit-field will be set to ‘1’ if this interrupt
has occurred since the last read of this register. The
“Detection of CP-Bit Error” interrupt will occur if the
receive DS3 Framer detects a CP-bit error in the
incoming DS3 Frame.
Bit 6—LOS Interrupt Status
This “Reset Upon Read” bit will be set to “1”, if the
Receive DS3 Framer has detected a
“Change in the LOS Status” condition, since the last
time this register was read. This bit-field will be as-
serted under either of the following two conditions:
When the Receive DS3 Framer detects the occur-
rence of an LOS Condition (e.g., the occurrence
of 180 consecutive “spaces” in the incoming DS3
data stream), and
When the Receive DS3 Framer detects the end
of an LOS Condition (e.g, when the Receive DS3
Framer detects 60 mark pulses in the last 180 bit
periods).
1.
2.
The local μP can determine the current state of the
LOS condition by reading bit 6 of the “Rx DS3 Con-
figuration and Status” Register (Address = 0Eh).
For more information in the “LOS of Signal (LOS)
Alarm, please see Section 7.1.2.3.1.
Bit 5—AIS Interrupt Status
This “Reset Upon Read” bit field will be set to “1”, if
the Receive DS3 Framer has detected a “Change in
the AIS” condition, since the last time this register
was read. This bit-field will be asserted under either
of the following two conditions:
1.
When the Receive DS3 Framer first detects an
AIS Condition in the incoming Bit 4—Idle Condi-
tion Interrupt Status, and
When the Receive DS3 Framer has detected the
end of an “AIS Condition”.
2.
The local μP can determine the current state of the
AIS condition by reading bit 7 of the “Rx DS3 Config-
uration and Status” Register (Address = 0Eh).
For more information on the “AIS Condition” please
see Sections 6.4.2.3 and 7.1.2.3.2.
Bit 4—Idle Interrupt Status
This “Reset Upon Read” bit-field is set to “1” when
the Receive DS3 Framer detects a “Change in the
Idle Condition” in the incoming DS3 data stream.
Specifically, the Receive DS3 Framer will assert this
bit-field under either of the following two conditions:
When the Receive DS3 Framer detects the onset
of the “Idle Condition”; and
When the Receive DS3 Framer detects the end
of the “Idle Condition”.
1.
2.
The local μP can determine the current state of the
Idle condition by reading bit 5 of the “Rx DS3 Config-
uration and Status” Register (Address = 0Eh).
For more information into the “Idle Condition”, please
see Section 7.1.2.3.3.
Bit 3—FERF Interrupt Status
This “Reset Upon Read” bit will be set to ‘1’ if the
Receive DS3 Framer has detected a “Change in the
Rx FERF” Condition, since the last time this register
was read.
This bit-field will be asserted under either of the
following two conditions.
When the Receive DS3 Framer first detects the
occurrence of an Rx FERF Condition (all X-bits
are set to ‘0’).
1.
Address = 11h, RxDS3 Interrupt Status Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
CP Bit Error
Interrupt Staus
LOS Interrupt
Status
AIS Interrupt
Status
Idle Interrupt
Status
FERF
Interrupt
Status
AIC Inter-
rupt Status
OOF
Interrupt
Status
P-Bit Error
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0