參數(shù)資料
型號(hào)： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號(hào)處理器
文件頁數(shù)： 92/173頁
文件大小： 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
92
DRAFT COPY
Lucent Technologies Inc.
Software Architecture
(continued)
Registers
(continued)
Register Settings
(continued)
Table 43. auc0 (Arithmetic Unit Control 0) Register
15
—
14
13
—
11
Reserved
10
9
8
7
6
5
—
4
3
—
2
1
—
0
P1SHFT[1:0]
FSAT
SHFT15
RAND
X=Y=
YCLR
ACLR[1:0]
ASAT[1:0]
P0SHFT[1:0]
Bit
Field
Value
00
01
10
11
—
0
1
Description
15—14
P1SHFT[1:0]
p1
not shifted.
p1
>>2.
p1
<<2.
p1
<<1.
Reserved—write with zero.
Disabled when zero.
Enable 32-bit saturation for the following results: the scaled outputs of the
p0
and
p1
registers, the intermediate result of the 3-input ADDER
, and the results of the
ALU/ACS, ADDER/ACS, and BMU.
p1
>>15 in F1E operations performs normally.
To support GSM-EFR,
p1
>>15 in F1E operations actually performs (
p1
>>16)<<1
clearing the least significant bit.
Enable pseudorandom sequence generator (PSG)
.
Reset and disable pseudorandom sequence generator (PSG).
Normal operation.
Data transfer statements that load the
y
register also load the
x
register with the same
value
§
.
The DAU clears
yl
if it loads
yh
.
The DAU leaves
yl
unchanged if it loads
yh
.
The DAU clears
a1l
if it loads
a1h
.
The DAU leaves
a1l
unchanged if it loads
a1h
.
The DAU clears
a0l
if it loads
a0h
.
The DAU leaves
a0l
unchanged if it loads
a0h
.
Enable
a1
saturation
on 32-bit overflow.
Disable
a1
saturation on 32-bit overflow.
Enable
a0
saturation
on 32-bit overflow.
Disable
a0
saturation on 32-bit overflow.
p0
not shifted.
p0
>>2.
p0
<<2.
p0
<<1.
13—11
10
Reserved
FSAT
9
SHFT15
0
1
8
RAND
0
1
0
1
7
X=Y=
6
YCLR
0
1
0
1
0
1
0
1
0
1
00
01
10
11
5
ACLR[1]
4
ACLR[0]
3
ASAT[1]
2
ASAT[0]
1—0
P0SHFT[1:0]
§
Saturation takes effect only if the ADDER has three input operands and there is no ALU/ACS operation in the same instruction.
After re-enabling the PSG by clearing RAND, the program must wait one instruction cycle before testing the heads or tails condition.
The following apply:
Instructions that explicitly load any part of the
x
register (i.e.,
x
,
xh
, or
xl
) take precedence over the X=Y= mode.
Instructions that load
yh
(but not
x
or
xh
) load
xh
with the same data. If YCLR is zero, the DAU clears
yl
and
xl
.
Instructions that load
yl
load
xl
with the same data and leave
yh
and
xh
unchanged.
If enabled, 32-bit saturation of the accumulator value occurs if the DAU stores the value to memory or to a register. Saturation also applies if the DAU
stores the low half, high half, or guard bits of the accumulator. There is no change to the contents stored in the accumulator; only the value stored to
memory or a register is saturated.
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