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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 31/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
31
Hardware Architecture
(continued)
External Memory Interface (EMI)
(continued)
Functional Timing
(continued)
Table 9
describes the computation of wait-states for read and write accesses (R
X
, R
Y
, and W) for each segment of
EMI storage, including the IORAM memories and ESIO memory-mapped registers.
Table 9. Wait-States
Access
X-memory read
Y-memory read
Write wait-states can be transparent to the core if the instruction that writes EMI storage is followed by non-EMI
instructions. If write wait-states are transparent, then the core continues execution while the EMI completes the
write operation. For example, the single write external wait-state in the following code segment is transparent and
does not stall the core execution:
*r0++=a0h
a0h=a0h+1
/* r0 points to IORAM, single-word write, one wait-state
/* 1-cycle instruction, no EMI access -- wait-state is transparent
*/
*/
READY Pin
The READY input pin permits an external device to extend the length of an EMI access cycle. The READY pin can
be used if the number of access cycles programmable in the
mwait
register (
Table 58 on page 101
) is insufficient,
or if the desired number of access cycles varies from access to access. To use the READY pin for a memory seg-
ment access, the access time field in the
mwait
register (IATIM[3:0], YATIM[3:0], or XATIM[3:0]) must be pro-
grammed to a value of four or greater and the corresponding RDYEN[2:0] field of
mwait
must be set. If the access
time field in
mwait
for the memory segment is less than four or if the RDYEN[2:0] field of
mwait
for the memory
segment is cleared, then the DSP16210 ignores the READY pin when accessing that segment. On device reset,
the RDYEN[2:0] fields are cleared, causing the DSP16210 to ignore the READY pin by default.
Figure 39 on
page 152
illustrates the operation of the READY pin.
The DSP16210 internally synchronizes the READY pin to the internal clock (CLK). READY must be asserted at
least five cycles (plus a setup time
1
) prior to the end of the external memory operation. The DSP16210 adds the
number of cycles that READY is asserted to the access time.
Segment
EROM
Number of Wait-States
(size
×
(XATIM[3:0] + 1) + misaligned)
(size
×
(YATIM[3:0] + 1) + misaligned)
(size
×
(IATIM[3:0] + 1) + misaligned)
(size
×
2 + misaligned)
(size
×
(YATIM[3:0] + 1) + misaligned)
(size
×
(IATIM[3:0] + 1) + misaligned)
(size + misaligned)
sizeis one for a 16-bit access and two for a 32-bit access. misalignedis one for a misaligned double-word access and zero for a single-word
access or an aligned double-word access.
Write wait-states can be transparent to the core if the EMI write instruction is followed by non-EMI instructions.
R
X
R
Y
ERAMHI or ERAMLO
IO
IORAM or ESIO
ERAMHI or ERAMLO
IO
IORAM or ESIO
Y-memory write
W
1. The READY pin setup time is t140 in
Table 108 on page 152
.
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