![](http://datasheet.mmic.net.cn/330000/DSP16210_datasheet_16391612/DSP16210_21.png)
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
21
Hardware Architecture
(continued)
Interrupts and Trap
(continued)
Table 4. Interrupt and User Trap Vector Table
Vector Description
Vector Address
Hexadecimal
vbase
+ 0x0
vbase
+ 0x4
vbase
+ 0x8
vbase
+ 0xC
vbase
+ 0x10
vbase
+ 0x14
vbase
+ 0x18
vbase
+ 0x1C
vbase
+ 0x20
vbase
+ 0x24
vbase
+ 0x28
vbase
+ 0x2C
vbase
+ 0x30
vbase
+ 0x34
vbase
+ 0x38
vbase
+ 0x3C
vbase
+ 0x40
vbase
+ 0x44
vbase
+ 0x48
vbase
+ 0x4C
vbase
+ 0x50
vbase
+ 0x54
vbase
+ 0x58
vbase
+ 0x5C
vbase
+ 0x60
vbase
+ 0x64
…
Priority
VEC[3:0]
Signals
—
0xD
0xE
—
—
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
—
—
—
—
0xC
0xC
0xC
Decimal
vbase
+ 0
vbase
+ 4
vbase
+ 8
vbase
+ 12
vbase
+ 16
vbase
+ 20
vbase
+ 24
vbase
+ 28
vbase
+ 32
vbase
+ 36
vbase
+ 40
vbase
+ 44
vbase
+ 48
vbase
+ 52
vbase
+ 56
vbase
+ 60
vbase
+ 64
vbase
+ 68
vbase
+ 72
vbase
+ 76
vbase
+ 80
vbase
+ 84
vbase
+ 88
vbase
+ 92
vbase
+ 96
vbase
+ 100
…
Reserved
—
PTRAP (driven by TRAP pin)
UTRAP (reserved for HDS)
Reserved
Reserved
MIBF0
MOBE0
MIBF1
MOBE1
INT0
INT1
INT2
INT3
TIME0
TIME1
EIFE
EOFE
ECOL
EIBF
EOBE
Reserved
Reserved
Reserved
Reserved
Software Interrupt 0 (
icall 0
)
Software Interrupt 1 (
icall 1
)
…
6—Highest
5
—
—
0—3
§
0—3
§
0—3
§
0—3
§
0—3
§
0—3
§
0—3
§
0—3
§
0—3
§
0—3
§
0—3
§
0—3
§
0—3
§
0—3
§
0—3
§
—
—
—
—
—
—
—
Software Interrupt 62 (
icall 62
)
Software Interrupt 63 (
icall 63
)
vbase
+ 0x158
vbase
+ 0x15C
vbase
+ 344
vbase
+ 348
—
—
0xC
0xC
vbase
contains the base address of the 352-word vector table.
The VEC[3:0] signals are multiplexed with the BIO signals IOBIT[7:4] onto the VEC[3:0]/IOBIT[7:4] pins (VEC0 corresponds to IOBIT7, VEC1
corresponds to IOBIT6, VEC2 corresponds to IOBIT5, and VEC3 corresponds to IOBIT4). VEC[3:0] defaults to 0xF (all ones) if the core is not
currently servicing an interrupt or a trap.
§ The programmer specifies the relative priority levels 0—3 for hardware interrupts via
inc0
and
inc1
(see the DSP16000 Digital Signal Proces-
sor CoreInformation Manual). Level 0 indicates a disabled interrupt. If the core simultaneously recognizes more than one interrupt with the
same assigned priority, it services the interrupt with the lowest vector address first.