Data Sheet
July 2000
DSP16210 Digital Signal Processor
118
DRAFT COPY
Lucent Technologies Inc.
Pin Information
(continued)
124, 125, 126,
127, 129, 130,
131, 132, 134,
135, 136, 137,
139, 140, 141,
142
10, 11, 12, 13
14
22
AB[15:0]
O
External Memory Address
Bus 15—0
3-state
logic low
INT[3:0]
IACK
STOP
I
External Interrupt Requests
Interrupt Acknowledge
STOP DSP Clocks
(negative assertion)
I/O TRAP/Breakpoint Indication
I
Device Reset (negative
assertion)
O
Programmable Clock Output
—
—
O
I
3-state
—
logic low
—
15
20
TRAP
RSTB
3-state
—
configured as input
—
18
CKO
INT0 = 0
(deasserted)
INT0 = 1
(asserted)
internal clock
(CLK = CKI)
3-state
internal clock
(CLK = CKI)
8
7
6
5
9
TCK
TMS
TDO
TDI
TRST
I
JTAG Test Clock
JTAG Test Mode Select
O
§
JTAG Test Data Output
I
JTAG Test Data Input
I
JTAG TAP Controller Reset
(negative assertion)
I
Input Clock
VEC0/IOBIT7 I/O Vectored Interrupt ID Bit
0/BIO Signal Bit 7
VEC1/IOBIT6 I/O Vectored Interrupt ID Bit
1/BIO Signal Bit 6
VEC2/IOBIT5 I/O Vectored Interrupt ID Bit
2/BIO Signal Bit 5
VEC3/IOBIT4 I/O Vectored Interrupt ID Bit
3/BIO Signal Bit 4
IOBIT3
I/O BIO Signal Bit 3
IOBIT2
I/O BIO Signal Bit 2
IOBIT1
I/O BIO Signal Bit 1
IOBIT0
I/O BIO Signal Bit 0
DOEN
I
SSIO Data Output Enable
DI
I
SSIO Data Input
ICK
I/O SSIO Input Clock
OBE
O
SSIO Output Buffer Empty
During and after reset, the internal clock is selected as the CKI input pin and the CKO output pin is selected as the internal clock.
This pin his internal pull-up circuitry.
3-states by JTAG control.
The
ioc
register (see
Table 54 on page 99
) is cleared after reset, including its EBIO field that controls the multiplexing of the VEC0/IOBIT7,
VEC1/IOBIT6, VDC2/IOBIT5, and VEC3/IOBIT4 pins. After reset, these pins are configured as the VEC[3:0] outputs and are logic high.
If unused, this pin must be pulled low through a 10 k
resistor to V
SS
.
§§ 3-states if RSTB = 0 or
PHIFC
[PCFIG] = 0.
—
—
—
—
—
—
—
—
—
—
I
3
24
CKI
—
—
3-state
logic high
25
3-state
logic high
26
3-state
logic high
27
3-state
logic high
29
30
31
32
33
41
39
44
3-state
3-state
3-state
3-state
—
—
3-state
3-state
configured as input
configured as input
configured as input
configured as input
—
—
configured as input
logic high
Table 80. Pin Descriptions
(continued)
TQFP Pin
Symbol
Type
Name/Function
Pin State During Reset
(RSTB = 0)
Pin State After
Reset
(RSTB 0
→
1)
§