參數(shù)資料
型號(hào)： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號(hào)處理器
文件頁數(shù)： 29/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
29
Hardware Architecture
(continued)
External Memory Interface (EMI)
(continued)
RWN Advance
The RWNADV field (
ioc
bit 3) controls the amount of delay from the beginning of a write access to the lowering of
the RWN pin. See
External Memory Interface
under
Timing Characteristics and Requirements
for details.
CKO Pin Configuration
The CKOSEL[2:0] field (
ioc
bits 7—5) configures the CKO pin as either the internal free-running clock (CLK), the
internal free-running clock held high during low-power standby mode, the output of the CKI input buffer, logic zero,
or logic one. See
Table 54 on page 99
.
Write Data Drive Delay
The write data delay (WDDLY) field (
ioc
bit 10) controls the amount of time that the EMI delays driving write data
onto the data bus (DB[15:0]). If WDDLY is cleared, the EMI drives the data bus approximately one half-cycle of
CLK after the beginning of the access
1
. If WDDLY is set, the EMI drives the data bus approximately one full cycle
of CLK after the beginning of the access
1
. As a result, setting WDDLY provides an additional delay of one half-
cycle for slower external memory. This additional delay is particularly useful if the external memory’s enable is
delayed (the corresponding DENB[2:0] bit is set).
If WDDLY is set, both the turn-on and turn-off delays for the data bus are increased
2
. Because the turn-off delay is
increased, it may be necessary to set the corresponding DENB[2:0] bit for any segments that are read immediately
after writing.
Functional Timing
The following definitions apply throughout:
Low
—an electrical level near ground corresponding to logic zero.
High
—an electrical level near V
DD
corresponding to logic one.
Assertion
—the changing of a signal to its active value.
Deassertion
—the changing of a signal to its inactive value.
EMI Storage
—storage that the EMI manages consisting of external memory, IORAM memory, and ESIO memory-
mapped registers.
EMI Instruction
—a DSP16210 instruction that accesses (reads or writes) EMI storage.
Non-EMI Instruction
—a DSP16210 instruction that does not access EMI storage.
CLK Period
—the time from rising edge to rising edge of the CLK clock; the duration of one single instruction
cycle. All EMI events occur on the rising edge of CLK. It is assumed that the CKO pin is programmed as CLK and
the remainder of this section uses the terms CLK and CKO interchangeably.
1. The beginning of the access occurs when the EMI drops RWN.
2. The data bus active interval is constant regardless of WDDLY.
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