參數(shù)資料
型號(hào)： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號(hào)處理器
文件頁數(shù)： 39/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
39
Hardware Architecture
(continued)
Enhanced Serial I/O Unit (ESIO)
(continued)
Simple Output Mode Processing.
The ESIO output
block operates in simple mode when OMODE (bit 10)
of the
OCR
register is set to 1. In this mode, the pro-
grammer must set the
OCVV
register to 0x0001. The
ESIO disables the output frame error (EOFE) and out-
put collision (ECOL) interrupts.
In simple mode, the ESIO supports double-buffered
8-bit and 16-bit LSB-first serial operation. Eight-bit
serial operation is selected by setting OSIZE (bit 9) of
the
OCR
register.
See
Figure 14 on page 38
for a diagram of the output
multiplexer structure. The program writes 8-bit or 16-bit
data into the
OMX0
register. (8-bit data must be right-
justified in
OMX0
). On the rising edge of the first OBC
clock after frame sync (OFS) detection, the data is
transferred from
OMX0
to the 16-bit parallel-to-serial
register (ODLD0 in
Figure 14
is asserted). During this
same OBC clock (illustrated as OBCQ0 in
Figure 14
),
the LSB of the data (B
0
) is applied to the EDO pin. On
each subsequent rising edge of OBC, the remaining
bits are applied to EDO. The simple mode output timing
diagram (for OLEV = 0, OSLEV = 0, and OSIZE = 0) is
illustrated in
Figure 53 on page 167
.
Frame Output Mode Processing.
The ESIO operates
in frame output mode when OMODE (bit 10) of the
OCR
register is cleared. (OMODE is cleared on reset.)
The ESIO multiplexes up to 16 channels of data onto a
serial stream consisting of a frame of 64, 128, 192, or
256 bits. The frame size is specified by OFRMSZ
(bits [13:12]) of the
OCR
register. The start of a new
frame is signaled by the rising edge of the output frame
sync (OFS). Serial data is captured by the falling edge
of the output bit clock (OBC) (see
Figure 13 on
page 37
).
See
Figure 14 on page 38
for a diagram of the output
multiplexed into EDO. The output section contains
16 double-buffered 16-bit parallel-to-serial output multi-
plexers. Each logical channel has a dedicated 16-bit
parallel write register (
OMX
0—15
) and has a dedi-
cated 16-bit shift register that transmits serial data for
that channel. Each shift register is clocked individually
by OBCQ[15:0], a qualified OBC bit clock that starts
when the internal bit counter matches the output logical
channel start bit specified by the corresponding
OCSB
0—7
register (see Table 13).
Table 13. Output Channel Start Bit Registers
OMX
0—15
are 16-bit write-only memory-mapped
registers that are written if the core writes to the corre-
sponding memory location (see
Table 12 on page 36
).
The ESIO asserts ODLDnfor logical channel n(see
Figure 14 on page 38
) to load the channel’s parallel-to-
serial register with the contents of the
OMXn
register.
All 16 parallel-to-serial registers are loaded simulta-
neously when the first frame sync (OFS) is asserted
following initialization of the output section. (See the
following discussion for a description of output section
initialization.) The parallel-to-serial register for
channel nis subsequently loaded (ODLDnasserted)
every 2, 4, 8, or 16 frames depending on the sample
length programmed for channel nvia
OCSL
0—1
(see
Table 61 on page 103
). This transfer permits the core
to write a new 16-bit word of channel data into
OMXn
while the old word is shifted out serially.
15
—
8
7
—
0
OCSB0
OCSB1
OCSB2
OCSB3
OCSB4
OCSB5
OCSB6
OCSB7
Channel 1
Channel 3
Channel 5
Channel 7
Channel 9
Channel 11
Channel 13
Channel 15
Channel 0
Channel 2
Channel 4
Channel 6
Channel 8
Channel 10
Channel 12
Channel 14
Field
Channel 0
to
Channel 15
Value
0x00
to
0xFF
Description
Start bit position for correspond-
ing logical output channel.
Ranges from 0 to 255.
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