參數(shù)資料
型號： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號處理器
文件頁數(shù)： 125/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
125
Signal Descriptions
(continued)
PHIF16 Interface
The PHIF16 interface implements a full 16-bit host
interface to standard microprocessors.
PB[15:0] —
PHIF16
Parallel I/O Data Bus:
Input/Out-
put. This 16-bit bidirectional bus is used to input data
to, or output data from, the PHIF16. It can be config-
ured as an 8-bit external bus where PB[15:8] are 3-
stated.
PCSN —
PHIF16
Peripheral Chip Select Not:
Nega-
tive assertion input. If PCSN is low, the data strobes
PIDS and PODS are enabled. If PCSN is high, the
DSP16210 ignores any activity on PIDS and PODS.
PBSEL — PHIF16 Peripheral Byte Select:
Input. The
assertion level is configurable in software via
PHIFC
[3].
Selects the high or low byte of PDX available for host
accesses (8-bit external mode).
PSTAT — PHIF16 Peripheral Status Register Select:
Input. If a logic 0, the PHIF16 outputs the PDX(out)
register on the PB bus. If a logic 1, the PHIF16 outputs
the contents of the
PSTAT
register on PB[7:0].
PIDS —
PHIF16
Input Data Strobe:
Input. Supports
either Intelor Motorolaprotocols. Configured by the
PHIFC
[PSTROBE] control register bit.
In Intelmode: Negative assertion. PIDS is pulled low
by an external device to indicate that data is available
on the PB bus. The DSP latches data on the PB bus on
the rising edge (low-to-high transition) of PIDS or
PCSN, whichever comes first.
In Motorolamode: PIDS (PRWN) functions as a
read/write strobe. The external device sets PIDS
(PRWN) to a logic 0 to indicate that data is available on
the PB bus (write operation by the external device). A
logic 1 on PIDS (PRWN) indicates an external read
operation by the external device.
PODS —
PHIF16
Output Data Strobe:
Input. Soft-
ware-configurable to support both Inteland Motorola
protocols:
In Intelmode: Negative assertion. When PODS is
pulled low by an external device, the DSP16210 places
the contents of the parallel output register, PDX(out),
onto the PB bus.
In Motorolamode: Software-configurable assertion
level. The external device uses PODS (PDS) as its
data strobe for both read and write operations.
PIBF —
PHIF16
Input Buffer Full:
Output. The asser-
tion level is configurable in software (
PHIFC
[4]). This
flag is cleared after reset, indicating an empty input
register PDX(in). PIBF is set immediately after the ris-
ing edge of PIDS or PCSN, indicating that data has
been latched into the PDX(in) register. When the
DSP16210 reads the contents of this register, emptying
the buffer, this flag is cleared. Configured in software
(
PHIFC
[5]), PIBF can become the logical OR of the
PIBF and POBE flags.
POBE — PHIF16
Output Buffer Empty:
Output. The
assertion level is configurable in software (
PHIFC
[4]).
This flag is set after reset, indicating an empty output
register PDX(out). POBE is set immediately after the
rising edge of PODS or PCSN, indicating that the data
in PDX(out) has been driven onto the PB bus. When
the DSP16210 writes to PDX(out), filling the buffer, this
flag is cleared.
JTAG Test Interface
The JTAG test interface has features that allow pro-
grams and data to be downloaded into the DSP via four
pins. This provides extensive test and diagnostic capa-
bility. In addition, internal circuitry allows the device to
be controlled through the JTAG port to provide on-chip,
in-circuit emulation. Lucent Technologies provides
hardware and software tools to interface to the on-chip
HDS via the JTAG port.
Note:
The DSP16210 provides all JTAG/IEEE1149.1
standard test capabilities including boundary
scan.
TDI — JTAG Test Data Input:
Serial input signal. All
serial-scanned data and instructions are input on this
pin. This pin has an internal pull-up resistor.
TDO — JTAG Test Data Output:
Serial output signal.
Serial-scanned data and status bits are output on this
pin.
TMS — JTAG
Test Mode Select:
Mode control signal
that, when combined with TCK, controls the scan oper-
ations. This pin has an internal pull-up resistor.
TCK — JTAG Test Clock:
Serial shift clock. This signal
clocks all data into the port through TDI, and out of the
port through TDO, and controls the port by latching the
TMS signal inside the state-machine controller.
TRST —
JTAG
TAP Controller Reset:
Negative
assertion. Test reset. When asserted low, resets JTAG
TAP controller. In an application environment, this pin
must be asserted prior to or concurrent with RSTB.
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