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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 6/173頁(yè) |
| 文件大小： | 2621K |
| 代理商： | DSP16210 |
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List of Tables
Tables
Page
Data Sheet
July 2000
DSP16210 Digital Signal Processor
6
DRAFT COPY
Lucent Technologies Inc.
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. ESIO Memory Map (Input Section) ................................................................................................... 32
Table 11. Input Channel Start Bit Registers...................................................................................................... 35
Table 12. ESIO Memory Map (Output Section)................................................................................................. 36
Table 13. Output Channel Start Bit Registers................................................................................................... 39
Table 14. ESIO Interrupts.................................................................................................................................. 41
Table 15. Instructions for Programming MIOU Registers.................................................................................. 42
Table 16. MIOU
0,1
16-Bit Directly Program-Accessible Registers................................................................. 43
Table 17. MIOU Write-Only Command-Accessible Registers........................................................................... 43
Table 18. MIOU
0,1
Command (
mcmd
0,1
) Register.................................................................................... 44
Table 19. Effect of Reset on MIOU Interrupts and Registers............................................................................ 44
Table 20. MIOU Interrupts................................................................................................................................. 46
Table 21. MIOU Command Latencies............................................................................................................... 48
Table 22. PHIF16 Output Function.................................................................................................................... 51
Table 23. PHIF16 Input Function ...................................................................................................................... 51
Table 24. PHIF16 Status (
PSTAT
) Register ..................................................................................................... 51
Table 25. BIO Operations.................................................................................................................................. 52
Table 26. BIO Flags .......................................................................................................................................... 52
Table 27. JTAG Boundary-Scan Register......................................................................................................... 55
Table 28. Clock Source Selection..................................................................................................................... 56
Table 29.
pllc
Field Values Nbits[2:0] and Mbits[2:0]........................................................................................ 58
Table 30. Example Calculation of M and N....................................................................................................... 60
Table 31. DSP16210 Instruction Groups........................................................................................................... 69
Table 32. Instruction Set Summary................................................................................................................... 71
Table 33. Notation Conventions for Instruction Set Descriptions...................................................................... 77
Table 34. Overall Replacement Table............................................................................................................... 78
Table 35. F1 Instruction Syntax......................................................................................................................... 81
Table 36. F1E Function Statement Syntax........................................................................................................ 83
Table 37. DSP16210 Conditional Mnemonics................................................................................................... 85
Table 38. Program-Accessible Registers by Type, Listed Alphabetically ......................................................... 88
Table 39. ESIO Memory-Mapped Registers ..................................................................................................... 90
Table 40. MIOU-Accessible Registers .............................................................................................................. 90
Table 41. DMA-Accessible Registers................................................................................................................ 90
Table 42.
alf
Register........................................................................................................................................ 91
Table 43.
auc0
(Arithmetic Unit Control 0) Register ......................................................................................... 92
Table 44.
auc1
(Arithmetic Unit Control 1) Register ......................................................................................... 93
Table 45.
cbit
(BIO Control) Register ............................................................................................................... 94
Table 46.
cstate
(Cache State) Register .......................................................................................................... 94
Table 47.
ICR
(ESIO Input Control) Register.................................................................................................... 95
Table 48.
ICSB
0—7
(ESIO Input Channel Start Bit) Registers...................................................................... 96
Table 49.
ICSL
0—1
(ESIO Input Channel Sample Length) Registers........................................................... 96
Table 50.
ICVV
(ESIO Input Channel Valid Vector) Register............................................................................ 96
Table 51.
ID
(JTAG Identification) Register....................................................................................................... 97
DSP16210 Block Diagram Legend.................................................................................................... 11
DSP16000 Core Block Diagram Legend........................................................................................... 17
State of Device Output and Bidirectional Pins During and After Reset............................................. 19
Interrupt and User Trap Vector Table................................................................................................ 21
Interrupt Control 0 and 1 (
inc0, inc1
) Registers ............................................................................... 22
Interrupt Status (
ins
) Register........................................................................................................... 22
Interrupt Request Clearing Latency................................................................................................... 23
Access Time and Wait-States........................................................................................................... 28
Wait-States........................................................................................................................................ 31
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