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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 30/173頁 |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
30
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
External Memory Interface (EMI)
(continued)
Functional Timing
(continued)
All DSP16210 external memory read and write operations consist of two parts:
1.
Active Part
: Lasts for the number of cycles programmed in the
mwait
register (IATIM[3:0], XATIM[3:0], or
YATIM[3:0]). Begins on a rising edge of CLK (CKO). Immediately after this rising edge:
a.The DSP16210 asserts the memory segment enable. If the leading edge of the memory segment enable is
delayed (the corresponding DENB[2:0] bit of
ioc
is set), the DSP16210 asserts the memory segment enable
one-half of a CLK period later.
b.The DSP16210 places the address on the address bus AB[15:0].
c. RWN becomes valid (high for a read, low for a write).
d.For a read operation, the DSP16210 3-states its data bus DB[15:0] drivers. For a write operation, the
DSP16210 delays driving the data bus by an interval determined by the WDDLY field (
ioc
bit 10). If
WDDLY = 0, the delay is approximately one half-cycle of CLK after RWN goes low. If WDDLY = 1, the delay is
approximately one cycle of CLK after RWN goes low.
2.
Finish Part
: Lasts for one cycle. Begins on a rising edge of CLK (CKO). Immediately after this rising edge:
a.The DSP16210 deasserts the memory segment enable.
b.For a read operation, the DSP16210 latches the data from DB[15:0]. For a write operation, the DSP16210 con-
tinues to drive data onto the data bus for an interval determined by the WDDLY field (
ioc
bit 10). If WDDLY = 0,
the DSP16210 drives the bus for approximately one half-cycle of CLK after the beginning of the finish part. If
WDDLY = 1, the DSP16210 drives the bus for approximately one cycle of CLK after the beginning of the finish
part.
As a consequence of the finish part of each memory operation, contention problems caused by back-to-back
assertion of different enables (one instruction with dual accesses) are avoided. Following the finish part, the
DSP16210 continues to drive the address bus with the last valid address until the beginning of the next external
read or write operation.
If an instruction
reads
from EMI storage, the number of wait-states incurred by the core during execution of that
instruction is R Ris computed as:
R = R
X
+ R
Y
where:
R
X
=Number of wait-states incurred from reading external X-memory
1
.
R
Y
=Number of wait-states incurred from reading external Y-memory, IORAM memory, or ESIO register.
If an instruction
writes
to EMI storage and is immediately followed by a second EMI instruction, wait-states are
incurred by the core during execution of the second
2
instruction. The number of wait-states is W:
where:
W= Number of wait-states incurred from writing external Y-memory, IORAM memory, or ESIO register.
1. Including possible instruction fetch.
2. Wait-states are incurred by the following instruction and not by the current instruction because the EMI internally buffers write data. In other
words, the core does not wait (as it does in the DSP1620) until the write data has been transferred to EMI storage. Instead, the core contin-
ues execution while the EMI waits to transfer the data to EMI storage on the next available memory cycle. A subsequent access to EMI stor-
age causes the core to wait until the prior write operation’s data has been transferred to storage.
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