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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 7/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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List of Tables
(continued)
Tables
Page
Lucent Technologies Inc.
DRAFT COPY
7
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Table 52.
inc
0—1
(
Interrupt Control) Registers............................................................................................. 97
Table 53.
ins
(Interrupt Status) Register........................................................................................................... 98
Table 54.
ioc
(I/O Configuration) Register........................................................................................................ 99
Table 55.
mcmd
0—1
(MIOU
0—1
Command) Registers .......................................................................... 100
Table 56.
miwp
0—1
(MIOU
0—1
IORAM Input Write Pointer) Registers.................................................. 100
Table 57.
morp
0—1
(MIOU
0—1
IORAM Output Read Pointer) Registers............................................... 101
Table 58.
mwait
(EMI Configuration) Register................................................................................................ 101
Table 59.
OCR
(ESIO Output Control) Register.............................................................................................. 102
Table 60.
OCSB
0—7
(ESIO Output Channel Start Bit) Registers ............................................................... 103
Table 61.
OCSL
0—1
(ESIO Output Channel Sample Length) Registers .................................................... 103
Table 62.
OCVV (
ESIO Output Channel Valid Vector) Register..................................................................... 103
Table 63.
PHIFC
(PHIF16 Control) Register................................................................................................... 104
Table 64.
pllc
(Phase-Lock Loop Control) Register........................................................................................ 105
Table 65.
powerc
(Power Control) Register................................................................................................... 106
Table 66.
PSTAT
(PHIF16 Status) Register ................................................................................................... 106
Table 67.
psw0
(Processor Status Word 0) Register...................................................................................... 107
Table 68.
psw1
(Processor Status Word 1) Register...................................................................................... 108
Table 69.
sbit
(BIO Status/Control) Register.................................................................................................. 109
Table 70.
SSIOC
(SSIO Control) Register...................................................................................................... 110
Table 71.
timer
0,1
(TIMER
0,1
Running Count) Register........................................................................... 111
Table 72.
timer
0,1
c
(TIMER
0,1
Control) Register ..................................................................................... 111
Table 73.
vsw
(Viterbi Support Word) Register .............................................................................................. 112
Table 74. Core Register States After Reset—40-bit Registers ....................................................................... 113
Table 75. Core Register States After Reset—32-bit Registers ....................................................................... 113
Table 76. Core Register States After Reset—20-bit Registers ....................................................................... 113
Table 77. Core Register States After Reset—16-bit Registers ....................................................................... 114
Table 78. Peripheral (Off-Core) Register States After Reset.......................................................................... 114
Table 79. RB Field........................................................................................................................................... 115
Table 80. Pin Descriptions .............................................................................................................................. 117
Table 81. Command Encoding for Boot Routines........................................................................................... 127
Table 82. Absolute Maximum Ratings............................................................................................................. 133
Table 83. Recommended Operating Conditions............................................................................................. 133
Table 84. Package Thermal Considerations ................................................................................................... 134
Table 85. Electrical Characteristics and Requirements................................................................................... 135
Table 86. Power Dissipation............................................................................................................................ 137
Table 87. Frequency Ranges for PLL Output.................................................................................................. 139
Table 88. PLL Loop Filter Settings and Lock-In Time..................................................................................... 139
Table 89. Wake-Up Latency............................................................................................................................ 140
Table 90. Timing Requirements for Input Clock.............................................................................................. 141
Table 91. Timing Characteristics for Input Clock and Output Clock................................................................ 141
Table 92. Timing Requirements for Powerup Reset and Device Reset.......................................................... 142
Table 93. Timing Characteristics for Powerup Reset and Device Reset......................................................... 142
Table 94. Timing Requirements for Reset Synchronization Timing................................................................ 143
Table 95. Timing Requirements for JTAG I/O................................................................................................. 144
Table 96. Timing Characteristics for JTAG I/O................................................................................................ 144
Table 97. Timing Requirements for Interrupt and Trap................................................................................... 145
Table 98. Timing Characteristics for Interrupt and Trap.................................................................................. 145
Table 99. Timing Requirements for BIO Input Read....................................................................................... 146
Table 100.Timing Characteristics for BIO Output............................................................................................. 146
Table 101.Timing Characteristics for Memory Enables and RWN................................................................... 147
Table 102.Timing Characteristics for External Memory Access (DENB = 0)....................................................148
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