參數(shù)資料
型號： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號處理器
文件頁數(shù)： 103/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
103
Software Architecture
(continued)
Registers
(continued)
Register Settings
(continued)
Table 60. OCSB
0—7
(ESIO Output Channel Start Bit) Registers
Note:
These registers are not directly program-accessible (memory-mapped at address 0xE0030 to 0xE0037).
Table 61. OCSL
0—1
(ESIO Output Channel Sample Length) Registers
Note:
These registers are used only in frame mode (
OCR
[OMODE] = 0) and are not directly program-accessible
(memory-mapped to addresses 0xE0038 and 0xE0039).
15
—
14
13
—
12
11
—
10
9
—
8
OCSL0
Channel 7
Channel 6
Channel 5
Channel 4
OCSL1
Channel 15 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 8
Table 62. OCVV (ESIO Output Channel Valid Vector) Register
Note:
This register is not directly program-accessible (memory-mapped to address 0xE003B). For simple mode,
enable only logical channel 0, i.e., set
OCVV
to 0x0001. For frame mode, the bits in
OCVV
must be packed,
i.e., channels must be allocated from 0 to 15 with no holes between valid channels. For example, if
OCVV
contains 0x00FF, then logical channels 0—7 are enabled and demultiplexed. A value of 0x08FF for
OCVV
is
invalid because the channels are not packed.
15
—
8
7
—
0
OCSB0
OCSB1
OCSB2
OCSB3
OCSB4
OCSB5
OCSB6
OCSB7
Channel 1
Channel 3
Channel 5
Channel 7
Channel 9
Channel 11
Channel 13
Channel 15
Channel 0
Channel 2
Channel 4
Channel 6
Channel 8
Channel 10
Channel 12
Channel 14
Field
Channel 0
to
Channel 15
Value
0x00
to
0xFF
Description
Start bit position for corresponding logical output channel. Ranges from 0 to 255.
7
—
6
5
—
4
3
—
2
1
—
0
Channel 3
Channel 2
Channel 1 Channel 0
Field
Channel 0
to
Channel 15
Value
00
01
10
11
Description
Output sample length is 1 bit (parallel-to-serial transfer rate is every 16 frames).
Output sample length is 2 bits (parallel-to-serial transfer rate is every 8 frames).
Output sample length is 4 bits (parallel-to-serial transfer rate is every 4 frames).
Output sample length is 8 bits (parallel-to-serial transfer rate is every 2 frames).
15
14
13
12
11
10
9
8
Channel 15
7
Channel 7
Channel 14
6
Channel 6
Channel 13
5
Channel 5
Channel 12
4
Channel 4
Channel 11
3
Channel 3
Channel 10
2
Channel 2
Channel 9 Channel 8
1
Channel 1 Channel 0
0
Field
Channel 0
to
Channel 15
Value
0
Description
Disable the corresponding logical output channel, i.e., do not multiplex the output data
stream for this logical channel.
Enable the corresponding logical output channel, i.e., multiplex the output data stream for
this logical channel.
1
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