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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 13/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
13
Hardware Architecture
(continued)
DSP16210 Architectural Overview
(continued)
Bit I/O (BIO) Unit
The BIO unit provides convenient and efficient monitor-
ing and control of eight individually configurable pins
(IOBIT[7:0]). When configured as outputs, the pins can
be individually set, cleared, or toggled. When config-
ured as inputs, individual pins or combinations of pins
can be tested for patterns. Flags returned by the BIO
are testable by conditional instructions. See
Bit
Input/Output Unit (BIO) beginning on page 52
for more
details.
Enhanced Serial I/O (ESIO) Unit
The ESIO is a programmable, hardware-managed,
passive, double-buffered full-duplex serial input/output
port designed to support glueless multichannel I/O pro-
cessing on a TDM (time-division multiplex) highway. In
simple mode, the ESIO supports data rates of up to
26 Mbits/s for a single channel with either 8-bit or 16-bit
data lengths. In frame mode, the ESIO processes up to
16 logical TDM channels with a data rate of up to
8.192 Mbits/s. For more information on the ESIO, see
Enhanced Serial I/O (ESIO) Unit beginning on
page 32
.
Simple Serial I/O (SSIO) Unit
The SSIO unit offers a full-duplex, double-buffered
external channel that operates at up to 26 Mbits/s.
Commercially available codecs and time-division multi-
plex channels can be interfaced to the SSIO with few, if
any, additional components.
The SSIO is a DMA peripheral managed by MIOU1.
See
Simple Serial I/O (SSIO) Unit beginning on
page 49
for more information.
Parallel Host Interface (PHIF16)
The PHIF16 is a DMA peripheral managed by MIOU0.
It is a passive 16-bit parallel port that can be configured
to interface to either an 8- or 16-bit external bus con-
taining other Lucent Technologies DSPs, microproces-
sors, or off-chip I/O devices. The PHIF16 port supports
either Motorolaor Intelprotocols.
When operating in the 16-bit external bus configura-
tion, PHIF16 can be programmed to swap high and low
bytes. When operating in 8-bit external bus configura-
tion, PHIF16 is accessed in either an 8-bit or 16-bit log-
ical mode. In 16-bit mode, the host selects either a high
or low byte access; in 8-bit mode, only the low byte is
accessed.
Additional software-programmable features allow for a
glueless host interface to microprocessors (see
Parallel
Host Interface (PHIF16) beginning on page 49
).
Timers
The two timers can be used to provide an interrupt,
either single or repetitive, at the expiration of a pro-
grammed interval. More than nine orders of magnitude
of interval selection are provided. The timers can be
stopped and restarted at any time under program con-
trol. See
Timers beginning on page 53
for more infor-
mation.
Test Access Port (JTAG)
The DSP16210 provides a test access port that con-
forms to IEEE 1149.1 (JTAG). The JTAG port provides
boundary scan test access and also controls the Hard-
ware Development System (HDS). See
JTAG Test Port
beginning on page 54
for details.
Hardware Development System (HDS)
The HDS is an on-chip hardware module available for
debugging assembly-language programs that execute
on the DSP16000 core in real-time. The main capability
of the HDS is in allowing controlled visibility into the
core’s state during program execution. The HDS is
enhanced with powerful debugging capabilities such as
complex breakpointing conditions, multiple
data/address watchpoint registers, and an intelligent
trace mechanism for recording discontinuities. See
Hardware Development System (HDS) beginning on
page 54
for details.
Pin Multiplexing
The upper four BIO pins (IOBIT[7:4]) are multiplexed
with the vectored interrupt identification pins
(VEC[3:0]). Specifically, VEC0 is multiplexed with
IOBIT7, VEC1 with IOBIT6, VEC2 with IOBIT5, and
VEC3 with IOBIT4. VEC[3:0] are connected to the
package pins and IOBIT[7:4] are disconnected immedi-
ately after device reset. To select IOBIT[7:4] to be con-
nected to these pins, the program must set EBIO (bit 8
of the
ioc
register).
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