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參數(shù)資料
| 型號： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號處理器 |
| 文件頁數(shù)： | 69/173頁 |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
69
Software Architecture
Instruction Set Quick Reference
The DSP16210 instruction set consists of both 16-bit and 32-bit wide instructions and resembles C-code. The fol-
lowing table defines the seven types of instructions. The assembler translates a code line into the most efficient
instruction(s). See
Table 33 on page 77
for instruction set notation conventions.
Table 31. DSP16210 Instruction Groups
Instruction
Group
(If Applicable)
MAC
F1
TRANSFER
F1E
TRANSFER
if CON
F1E
F Title
Description
The powerful MAC instruction group is the primary group of instructions
used for signal processing. Up to two data transfers can be combined with
up to four parallel DAU operations in a single MAC instruction to execute
simultaneously
. The DAU operation combinations include (but are not lim-
ited to) either a dual-MAC
operation, an ALU operation and a BMU opera-
tion, or an ALU/ACS operation and an ADDER operation. The F1E
instructions that do not include a transfer statement can execute condition-
ally based on the state of flags.
Special functions include rounding, negation, absolute value, and fixed
arithmetic left and right shift operations. The operands are an accumulator,
another DAU register, or an accumulator and another DAU register. Some
special function instructions increment counters. Special functions execute
conditionally based on the state of flags.
ALU instructions operate on two accumulators or on an accumulator and
another DAU register. Many instructions can also operate on an accumula-
tor and an immediate data word. The ALU operations are add, subtract, log-
ical AND, logical OR, exclusive OR, maximum, minimum, and divide-
step. Some F3E instructions include a parallel ADDER operation. The F3E
instructions can execute conditionally based on the state of flags.
Full barrel shifting, exponent computation, normalization computation, bit-
field extraction or insertion, and data shuffling between two accumulators
are BMU operations that act on the accumulators. BMU operations are con-
trolled by an accumulator, an auxiliary register, or a 16-bit immediate
value. The F4E instructions can execute conditionally based on the state of
flags.
Data move instructions transfer data between two registers or between a
register and memory. This instruction group also supports immediate loads
of registers, conditional register-to-register moves, pipeline block moves,
and specialized stack operations. Pointer arithmetic instructions perform
arithmetic on data pointers and do not perform a memory access.
The control instruction group contains branch and call subroutine instruc-
tions with either a 20-bit absolute address or a 12-bit or 16-bit PC-relative
address. This group also includes instructions to enable and disable
interrupts. Some control instructions can execute conditionally based on
the state of processor flags.
Cache instructions implement low-overhead loops by loading a set of up to
31 instructions into cache memory and repetitively executing them as many
as 2
16
– 1 times.
Executes in one instruction cycle in most cases.
A dual-MAC operation consists of two multiplies and an add or subtract operation by the ALU, an add or subtract operation by the ADDER, or
both.
Special
Function
if CON
F2
ifc CON F2
if CON
F2E
ifc CON
F2E
ALU
F3
if CON
F3E
BMU
F4
if CON
F4E
Data Move
and
Pointer
Arithmetic
—
Control
—
Cache
—
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