參數(shù)資料
型號: DSP16210
英文描述: TVS 400W 6.5V UNIDIRECT SMA
中文描述: DSP16210數(shù)字信號處理器
文件頁數(shù): 145/173頁
文件大?。?/td> 2621K
代理商: DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
145
Timing Characteristics and Requirements
(continued)
Interrupt and Trap
CKO is free-running.
INT is one of INT[3:0] or TRAP
Figure 32. Interrupt and Trap Timing Diagram
Table 97. Timing Requirements for Interrupt and Trap
Note:
Interrupt is asserted during an interruptible instruction and no other pending interrupts.
Abbreviated Reference
t21
t22
Parameter
Min
8
2T
Max
Unit
ns
ns
Interrupt Setup (high to low)
INT/TRAP Assertion Time (high to low)
T = internal clock period (CLK).
Table 98. Timing Characteristics for Interrupt and Trap
Note:
Interrupt is asserted during an interruptible instruction and no other pending interrupts.
Abbreviated Reference
t23
t24
t25
t26
Parameter
Min
Max
10
10
10
10
Unit
ns
ns
ns
ns
IACK Valid Time (low to high)
VEC Valid Time (high to low)
IACK Invalid Time (low to low)
VEC Invalid Time (high to high)
5-4018(F).c
CKO
INT
t21
V
OH
V
OL
V
IH
V
IL
t22
IACK
V
OH
V
OL
VEC[3:0]
V
OH
V
OL
t23
t24
3T
t25
t26
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