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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 52/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
52
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Bit Input/Output Unit (BIO)
The BIO controls the directions of eight bidirectional
control I/O pins, IOBIT[7:0]. If a pin is configured as an
output, it can be individually set, cleared, or toggled. If
a pin is configured as an input, it can be read and/or
tested.
The lower half of the
sbit
register (see
Table 69 on
page 109
) contains current values (VALUE[7:0]) of the
eight bidirectional pins IOBIT[7:0]. The upper half of the
sbit
register (DIREC[7:0]) controls the direction of each
of the pins. A logic 1 configures the corresponding pin
as an output; a logic 0 configures it as an input. The
upper half of the
sbit
register is cleared upon reset.
The
cbit
register (see
Table 45 on page 94
) contains
two 8-bit fields, MODE/MASK[7:0] and DATA/PAT[7:0].
The meaning of a bit in either field depends on whether
it has been configured as an input or an output in
sbit
.
If a pin has been configured to be an output, the mean-
ings are MODE and DATA. For an input, the meanings
are MASK and PAT(tern). Table 25 shows the function-
ality of the MODE/MASK and DATA/PAT bits based on
the direction selected for the associated IOBIT pin.
Those pins that have been configured as inputs can be
individually tested for 1 or 0. For those inputs that are
being tested, there are four flags produced: ALLT (all
true), ALLF (all false), SOMET (some true), and
SOMEF (some false). Table 26 summarizes these
flags, which can be used for conditional instructions
(see
Table 37 on page 85
). The state of these flags
can be tested, saved, or restored by reading or writing
bits 0 to 3 of the
alf
register (see
Table 42 on page 91
).
In input mode, the IOBIT[7:0] inputs are synchronized
to the internal DSP clock (CLK) before the flags are
generated or the input data is transferred to the core
through the
sbit
register. In output mode, the flags are
updated each time the
cbit
register is written.
If a BIO pin is switched from being configured as an
output to being configured as an input and then back to
being configured as an output, the pin retains the previ-
ous output value. After writing
sbit
to change a pin
from an output to an input, one instruction cycle of
latency is required before the
sbit
VALUE field is
updated. If a pin is configured as an output and
cbit
is
written to change the output value, two cycles of
latency are required before the
sbit
VALUE field is
updated to reflect the change to
cbit
.
Table 26. BIO Flags
Table 25. BIO Operations
DIREC[n]
0
≤
n
≤
7.
MODE/
MASK[n]
0
0
1
DATA/
PAT[n]
0
1
0
Action
1 (Output)
1 (Output)
1 (Output)
Clear
Set
No
Change
Toggle
No Test
No Test
Test for
Zero
Test for
One
1 (Output)
0 (Input)
0 (Input)
0 (Input)
1
0
0
1
1
0
1
0
0 (Input)
1
1
Condition
SOMEF
(alf[3])
0
1
1
SOMET
(alf[2])
1
0
1
ALLF
(alf[1])
0
1
0
ALLT
(alf[0])
1
0
0
All or some of the IOBIT[7:0]
pins are configured as
inputs
.
All tested inputs match the pattern
.
No tested inputs match the pattern
§
.
Some (but not all) of the tested inputs match
the pattern
.
No inputs are tested
.
0
0
0
0
1
1
1
1
All IOBIT[7:0] pins are configured as outputs
§§
.
§
For at least one pin, IOBIT[n] with DIREC[n] = 0 and MASK[n] = 1, IOBIT[n] = PAT[n], and for at least one pin IOBIT[n] with DIREC[n] = 0 and
MASK[n] = 1, IOBIT[n]
≠
PAT[n].
For all pins, IOBIT[n] with DIREC[n] = 0, MASK[n] is 0.
§§ Bits DIREC[7:0] are all ones.
For at least one pin IOBIT[n], DIREC[n] = 0.
For every pin, IOBIT[n] with DIREC[n] = 0 and MASK[n] = 1, IOBIT[n] = PAT[n].
For every pin, IOBIT[n] with DIREC[n] = 0 and MASK[n] = 1, IOBIT[n]
≠
PAT[n].
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