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參數(shù)資料
| 型號： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號處理器 |
| 文件頁數(shù)： | 46/173頁 |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
46
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Modular I/O Units (MIOUs)
(continued)
Length Counters and MIOU Interrupts
ILEN
0,1
is the input length counter register that contains a 12-bit two’s complement number. It
contains an initial
value of –1 following reset or execution of a RESET
0,1
command. Execution of an ILEN
0,1
_UP command
adds the command’s parameter value to
ILEN
0,1
and causes MIOU
0,1
to begin input processing. MIOU
0,1
decrements
ILEN
0,1
each time it transfers an input sample from the peripheral to the IORAM
0,1
. The input
buffer full interrupt MIBF
0,1
is asserted when
ILEN
0,1
makes a transition from 0 to –1. This provides a means
of input flow control (see
DMA Input Flow Control
for more information). After MIBF
0,1
is asserted, MIOU
0,1
continues input processing and continues to decrement
ILEN
0,1
so that core and MIOU
0,1
processing is con-
current. The software must ensure that the content of
ILEN
0,1
is within the range +1024 to –1023. If
ILEN
0,1
exceeds this range, MIBF
0,1
is not valid, the MIOU
0,1
operation is undefined, and the software must execute a
RESET
0,1
command.
OLEN
0,1
is the output length counter register that contains an 11-bit unsigned number. It
contains an initial
value of 0 following reset or execution of a RESET
0,1
command. Execution of an OLEN
0,1
_UP command
adds the command’s parameter value to
OLEN
0,1
. If an initial ILEN
0,1
_UP command
1
has been previously
executed, the execution of OLEN
0,1
_UP causes MIOU
0,1
to begin output processing. If an initial
ILEN
0,1
_UP command has not been previously executed, then MIOU
0,1
does not begin output processing
until an ILEN
0,1
_UP command is issued. MIOU
0,1
decrements
OLEN
0,1
each time it transfers an output
sample from the IORAM
0,1
to the peripheral. The output buffer empty interrupt MOBE
0,1
is asserted and
MIOU
0,1
stops output processing when
OLEN
0,1
reaches 0. This provides a means of output flow control
(see
DMA Output Flow Control
for more information). The software must ensure that the contents of
OLEN
0,1
does not exceed 1024. If
OLEN
0,1
exceeds 1024, the MIOU
0,1
operation is undefined and the software must
execute a RESET
0,1
command.
Table 20
summarizes the MIOU interrupts MIBF
0,1
and MOBE
0,1
.
Table 20. MIOU Interrupts
Interrupt
MIBF
0,1
DMA Input Flow Control
Prior to configuring the MIOU input control registers (
miwp
0,1
, IBAS
0,1
, and ILIM
0,1
), the user’s software
must execute the RESET
0,1
command. This ensures that MIOU
0,1
peripheral service operations do not dis-
turb the register configuration. The software then executes an ILEN
0,1
_UP command to begin input operations.
The core and MIOU
0,1
cooperate to manage the input flow by updating
ILEN
0,1
. Typically, software initializes
ILEN
0,1
with the logical buffer size (number of samples), L1, of the first input transaction. When MIBF
0,1
is
asserted, software processes the first logical buffer (using L1) and issues an ILEN
0,1
_UP command with a
parameter equal to the number of samples in the next logical buffer (L2). MIOU
0,1
and core processing are con-
current, so the MIOU
0,1
fills the new buffer while the first buffer is processed by the core.
1. The initial ILEN
0,1
_UP command after reset activates MIOU
0,1
and its attached peripheral.
Condition to Assert
ILEN
0,1
decrements below zero.
Condition to Clear
Software issues ILEN
0,1
_UP command resulting in
ILEN
0,1
≥
0.
Software issues a RESET
0,1
command. Pin is reset.
Software issues OLEN
0,1
_UP command resulting in
OLEN
0,1
> 0.
MOBE
0,1
OLEN
0,1
decrements to zero.
Software issues a RESET
0,1
command.
Pin reset.
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