Data Sheet
July 2000
DSP16210 Digital Signal Processor
74
DRAFT COPY
Lucent Technologies Inc.
Software Architecture
(continued)
Instruction Set Quick Reference
(continued)
Table 32. Instruction Set Summary
(continued)
BMU Group
aD=aS SHIFT
aTEh,arM
aDh=exp(aTE)
aD=norm(aS,
aTEh,arM
)
aD=extracts(aS,aTEh)
aD=extractz(aS,aTEh)
aD=inserts(aS,aTEh)
aD=insertz(aS,aTEh)
aD=extract(aS,arM)
aD=extracts(aS,arM)
aD=extractz(aS,arM)
aD=insert(aS,arM)
aD=inserts(aS,arM)
aD=insertz(aS,arM)
aD=aS:aTE
aDE=extract(aSE,IM8W,IM8O)
aDE=extracts(aSE,IM8W,IM8O)
aDE=extractz(aSE,IM8W,IM8O)
aDE=insert(aSE,IM8W,IM8O)
aDE=inserts(aSE,IM8W,IM8O)
aDE=insertz(aSE,IM8W,IM8O)
aDE=aSE SHIFT IM16
if CON
aDE=aSE SHIFT
aTEh,arM
if CON
aDEh=exp(aTE)
if CON
aDE=norm(aSE,
aTEh,arM
)
if CON
aDE=extracts(aSE,aTEh)
if CON
aDE=extractz(aSE,aTEh)
if CON
aDE=inserts(aSE,aTEh)
if CON
aDE=insertz(aSE,aTEh)
if CON
aDE=extract(aSE,arM)
if CON
aDE=extracts(aSE,arM)
if CON
aDE=extractz(aSE,arM)
if CON
aDE=insert(aSE,arM)
if CON
aDE=inserts(aSE,arM)
if CON
aDE=insertz(aSE,arM)
if CON
aDE=aSE:aTE
X
C
is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-
tion types and can only be avoided by use of the cache.
For this transfer, the postincrement options
*rME
and
*rME––
are not available
for double-word loads.
§ The – (40-bit subtraction) operation is encoded as
aDE=aSE+IM16
with the IM16 value negated.
For conditional branch instructions, the execution time is two cycles if the branch is not taken.
The instruction performs the same function whether or not
near
(optional) is included.
§§ Not including the N instructions.
(F4)
(F4)
(F4)
(F4)
szlme
szlme
szlme
szlme
1
1
1
(F4)
szlme
(F4)
szlme
(F4)
szlme
(F4)
szlm–
szlme
(F4 with immediate)
1
1
2
(F4 with immediate)
szlme
(F4 with immediate)
szlme
szlme
szlme
szlme
szlme
(F4E)
(F4E)
(F4E)
(F4E)
1
1
2
(F4E)
szlme
(F4E)
szlme
(F4E)
szlme
(F4E)
szlm–
Instruction
Flags
szlme
Cycles
Out
Words
In