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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 4/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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List of Figures
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Figures
Page
4
DRAFT COPY
Lucent Technologies Inc.
Figure 1. DSP16210 Block Diagram..................................................................................................................10
Figure 2. DSP16000 Core Block Diagram.........................................................................................................16
Figure 3. INT[3:0] and TRAP Timing.................................................................................................................24
Figure 4. Interleaved Internal DPRAM...............................................................................................................25
Figure 5. X-Memory Space Memory Map .........................................................................................................25
Figure 6. Y-Memory Space Memory Maps........................................................................................................26
Figure 7. Input Control Signal Conditioning.......................................................................................................33
Figure 8. Frame Sync Timing with ILEV = ISLEV = 0 and ISDLY = 1................................................................33
Figure 9. Input Functional Timing......................................................................................................................33
Figure 10. Input Demultiplexer (
IDMX
) and Register File Structure ....................................................................34
Figure 11. Serial Input Clocking Example ...........................................................................................................35
Figure 12. Output Control Signal Conditioning....................................................................................................37
Figure 13. Output Functional Timing...................................................................................................................37
Figure 14. Output Multiplexer (
OMX
) and Register File Structure.......................................................................38
Figure 15. Serial Output Clocking Example.........................................................................................................40
Figure 16. Modular I/O Units ...............................................................................................................................42
Figure 17. Input and Output Buffer Configuration in IORAM
0,1
.......................................................................45
Figure 18. Clock Synthesizer (PLL) Block Diagram.............................................................................................56
Figure 19. Internal Clock Selection and Disable Logic........................................................................................57
Figure 20. Allowable States and State Changes of
pllc
Register Fields.............................................................59
Figure 21. Power Management and Clock Distribution........................................................................................62
Figure 22. Interpretation of the Instruction Set Summary Table..........................................................................70
Figure 23. DSP16210 Program-Accessible Registers.........................................................................................87
Figure 24. DSP16210 144-Pin TQFP Pin Diagram (Top View) ........................................................................116
Figure 25. DSP16210 Pinout by Interface.........................................................................................................121
Figure 26. Plot of V
OH
vs. I
OH
Under Typical Operating Conditions ..................................................................136
Figure 27. Plot of V
OL
vs. I
OL
Under Typical Operating Conditions....................................................................136
Figure 28. I/O Clock Timing Diagram ...............................................................................................................141
Figure 29. Powerup Reset and Device Reset Timing Diagram ........................................................................142
Figure 30. Reset Synchronization Timing..........................................................................................................143
Figure 31. JTAG I/O Timing Diagram ................................................................................................................144
Figure 32. Interrupt and Trap Timing Diagram ................................................................................................145
Figure 33. Write Outputs Followed by Read Inputs (
cbit = IMMEDIATE; a1 = sbit
) Timing Characteristics....146
Figure 34. Enable Transition Timing..................................................................................................................147
Figure 35. External Memory Data Read Timing Diagram (No Delayed Enable) ..............................................148
Figure 36. External Memory Data Read Timing Diagram (Delayed Enable) ....................................................149
Figure 37. External Memory Data Write Timing Diagram (DENB2 = 0, DENB1 = 0, DENB0 = 0)....................150
Figure 38. External Memory Data Write Timing Diagram (DENB2 = 0, DENB1 = 1, DENB0 = 0)....................151
Figure 39. READY Extended Read Cycle Timing..............................................................................................152
Figure 40. PHIF16 IntelMode Signaling (Read and Write) Timing Diagram.....................................................153
Figure 41. PHIF16 IntelMode Signaling (Pulse Period and Flags) Timing Diagram ......................................155
Figure 42. PHIF16 MotorolaMode Signaling (Read and Write) Timing Diagram..............................................156
Figure 43. PHIF16 MotorolaMode Signaling (Pulse Period and Flags) Timing Diagram .................................158
Figure 44. PHIF16 Intelor MotorolaMode Signaling (Status Register Read) Timing Diagram .......................159
Figure 45. PIBF and POBE Reset Timing Diagram ..........................................................................................160
Figure 46. POBE and PIBF Disable Timing Diagram........................................................................................160
Figure 47. SSIO Passive Mode Input Timing Diagram .....................................................................................161
Figure 48. SSIO Active Mode Input Timing Diagram ........................................................................................162
Figure 49. SSIO Passive Mode Output Timing Diagram ..................................................................................163
Figure 50. SSIO Active Mode Output Timing Diagram......................................................................................164
Figure 51. Serial I/O Active Mode Clock Timing................................................................................................165
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