參數(shù)資料
型號： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號處理器
文件頁數(shù)： 111/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
111
Software Architecture
(continued)
Registers
(continued)
Register Settings
(continued)
Table 71. timer
0,1
(TIMER
0,1
Running Count) Register
Table 72. timer
0,1
c (TIMER
0,1
Control) Register
15—7
6
Reserved
PWR_DWN
Bits 15—0
Running Count for TIMER
0,1
Field
Description
Read
timer
0,1
for current output of down counter. Write
timer
0,1
to load down
counter and period register
.
R/W
0
To read or write this register, TIMER
0,1
must be powered up, i.e.,
timer
0,1
c
[PWR_DWN] and
powerc
[TIMER
0,1
] must both be cleared.
The period register is used if
timer
0,1
c
[RELOAD] is set—the timer automatically reloads the down counter from the period register after the
counter reaches zero and continues decrementing the counter indefinitely
.
R/W
Reset Value
5
4
3—0
RELOAD
COUNT
PRESCALE[3:0]
Bit
Field
Reserved
PWR_DWN
Value
0
0
1
0
1
Description
15—7
6
Reserved—write with zero.
Power up the timer
.
Power down the timer
.
Stop decrementing the down counter after it reaches zero.
Automatically reload the down counter from the period register after the
counter reaches zero and continue decrementing the counter indefinitely.
Hold the down counter at its current value, i.e., stop the timer.
Decrement the down counter, i.e., run the timer.
Controls the counter prescaler to determine the fre-
quency of the timer, i.e., the frequency of the clock
applied to the timer down counter. This frequency is a
ratio of the internal clock frequency f
CLK
:
5
RELOAD
4
COUNT
0
1
3—0
PRESCALE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
f
CLK
/2
f
CLK
/4
f
CLK
/8
f
CLK
/16
f
CLK
/32
f
CLK
/64
f
CLK
/128
f
CLK
/256
f
CLK
/512
f
CLK
/1024
f
CLK
/2048
f
CLK
/4096
f
CLK
/8192
f
CLK
/16384
f
CLK
/32768
f
CLK
/65536
Except if
powerc
[TIMER
0,1
] is set.
Except if
powerc
[TIMER
0,1
] is cleared. If TIMER
0,1
is powered down, then
timer
0,1
cannot be read or written. While the timer is pow-
ered down, the state of the down counter and period register remain unchanged.
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