參數(shù)資料
型號(hào): DSP16210
英文描述: TVS 400W 6.5V UNIDIRECT SMA
中文描述: DSP16210數(shù)字信號(hào)處理器
文件頁數(shù): 169/173頁
文件大?。?/td> 2621K
代理商: DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
169
Timing Characteristics and Requirements
(continued)
Enhanced Serial I/O
(continued)
Figure 55. Frame Mode Output Timing Diagram
Note:
Frame mode with OMODE = 0, OLEV = 0, OSIZE = 0, OSLEV = 0, and OFRMSZ[1:0] = N.
Table 135. Timing Requirements for ESIO Frame Output Mode
Abbreviated Reference
t200
t201
t202
t203
t205
Parameter
Min
122
16
16
8
8
Max
Unit
ns
ns
ns
ns
ns
EOBC Bit Clock Period (high to high)
EOBC Bit Clock High Time (high to low)
EOBC Bit Clock Low Time (low to high)
EOFS Hold Time (high to low or high to high)
EOFS Setup Time (low to high or high to high)
Table 136. Timing Characteristics for ESIO Frame Output Mode
Abbreviated Reference
t209
t210
t211
t213
Parameter
Min
Max
20
20
20
20
Unit
ns
ns
ns
ns
EDO is active after the t209 interval or t211 interval, whichever occurs last.
EDO Data Delay (high to valid)
EOBE Delay (low to high)
EOEB External Enable Delay (low to active)
EDO 3-state Delay (high to 3-state)
t200
t201
t202
t209
t211
EOBC
EOFS
EDO
V
IH –
V
IL –
V
OH –
V
OL –
B0
B1
B
N– 1
EOBEV
OH –
t213
B
N – 2
B0
t203
t205
EOEB
V
IH –
V
IL –
V
IH –
V
IL –
t210
t203
t205
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