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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 61/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
61
Hardware Architecture
(continued)
Power Management
There are three different control mechanisms for put-
ting the DSP16210 into low-power modes: the
powerc
control register, the STOP pin, and the AWAIT bit in the
alf
register (standby mode).
Note:
If the PLL is enabled (
pllc
[15] = 1), it remains
running and consumes power even if the
DSP16210 is in a low-power mode. For maxi-
mum power savings, disable the PLL before
entering a low-power mode.
The powerc Control Register Bits
The
powerc
register has 11 bits (5 bits are reserved)
that power down various portions of the chip and select
the source of the internal clock (CLK):
SLOWCLK: If the program sets the SLOWCLK bit and
clears the PLLSEL bit (
pllc
[14]), an internal ring oscilla-
tor is selected as the source for CLK instead of the CKI
pin or the PLL. If the SLOWCLK bit is cleared, the ring
oscillator is powered down. Switching of the clocks is
synchronized so that no partial or short clock pulses
occur. Two
nop
instructions
should follow any instruc-
tion that changes the state of SLOWCLK.
NOCK: If the program sets the NOCK bit, the
DSP16210 synchronously turns off CLK (regardless of
whether its source is provided by the CKI pin, the PLL,
or the internal ring oscillator) and stops program execu-
tion. Two
nop
instructions should follow any instruction
that sets NOCK. The NOCK bit can be cleared by
asserting the INT0 or INT1 pin (if the INT0EN or
INT1EN bit is set). Clearing the NOCK bit in this man-
ner allows the stopped program to resume execution
from where it left off without any loss of state. If
INT0EN or INT1EN is set, it is recommended that the
programmer disable the corresponding interrupt in the
inc0
register before setting NOCK to avoid an uninten-
tional interrupt due to the subsequent assertion of the
INT0 or INT1 pin. After the stopped program resumes,
it should clear the corresponding INT0/INT1 interrupt
by writing to the
ins
register (see
Clearing Interrupts on
page 23
). Resetting the DSP16210 by asserting the
RSTB pin also clears the NOCK bit, but the stopped
program cannot resume execution.
INT0EN: This bit allows the INT0 pin to asynchronously
clear the NOCK bit as described above.
INT1EN: This bit allows the INT1 pin to asynchronously
clear the NOCK bit as described above.
The following control bits, if set, individually power
down the peripheral units, further reducing the power
consumption during low-power standby mode.
Figure 21 on page 62
illustrates the effect of these bits.
ESIO: This is a powerdown signal to the ESIO unit. It
disables the clock input to the unit, thus eliminating any
standby power associated with the ESIO. Since the
gating of the clocks can result in incomplete transac-
tions, this option can only be used in applications
where the ESIO is not used or when reset is used to re-
enable the ESIO unit. Otherwise, the first transaction
after re-enabling the unit could be corrupted.
SSIO: This bit powers down the SSIO in the same way
ESIO powers down the ESIO unit.
MIOU1: This is a powerdown signal to the MIOU1. It
disables the clock input to the unit, thus eliminating any
standby power associated with the MIOU1. Since the
gating of the clocks can result in incomplete transac-
tions, this option can only be used in applications
where the MIOU1 is not used, or when reset is used to
re-enable the MIOU1 unit. Since MIOU1 and SSIO
operate independently of each other, the MIOU1 can
be powered down while SSIO remains active. Before
powering down MIOU1, the program should poll the
MBUSY1 flag (see
Table 37 on page 85
) to ensure that
all output activity is complete.
PHIF16: This is a powerdown signal to the PHIF16 unit.
It disables the clock input to the unit, thus eliminating
any standby power associated with the PHIF16. Since
the gating of the clocks can result in incomplete trans-
actions, this option can only be used in applications
where the PHIF16 is not used, or when reset is used to
re-enable the PHIF16 unit.
MIOU0: This is a powerdown signal to the MIOU0. It
disables the clock input to the unit, thus eliminating any
standby power associated with the MIOU0. Since the
gating of the clocks can result in incomplete transac-
tions, this option can only be used in applications
where the MIOU0 is not used, or when reset is used to
re-enable the MIOU0 unit. Since MIOU0 and PHIF16
operate independently of each other, the MIOU0 can
be powered down while PHIF16 remains active. Before
powering down MIOU0, the program should poll the
MBUSY0 flag (see
Table 37 on page 85
) to ensure that
all output activity is complete.
TIMER0: This is a TIMER0 disable signal that disables
the clock input to the TIMER0 unit. Its function is identi-
cal to the DISABLE0 field of the
timer0c
control regis-
ter. Writing a 0 to TIMER0 in the
powerc
register field
will continue TIMER0 operation.
TIMER1: This bit disables the clock input to the
TIMER1 unit the same way TIMER0 disables the
TIMER0 unit.
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