Data Sheet
July 2000
DSP16210 Digital Signal Processor
66
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Power Management
(continued)
Low-Power Mode Standby with Slow Internal Clock, PLL Enabled and Not Selected
. The PLL is enabled to
run at 100 MHz, assuming a constant CKI input clock of 10 MHz. Prior to entering low-power standby mode
1
by
setting the AWAIT bit (
alf
[15]), the program reduces power by turning off all the peripherals, holding the CKO pin
low, and selecting the slow internal clock as the clock source. The PLL remains enabled during standby mode and
continues to dissipate power.
di
pllc=0xa9f2
/* Globally disable interrupts for PLL lock.
/* pllc[15]=1 enables the PLL to run at 100 MHz
/* with CKI=10 MHz. CKI must remain running.
/* Assure time for PLL to lock
if lock goto select_pll
goto pll_buzz
*/
*/
*/
*/
pll_buzz:
select_pll:
pllc=0xe9f2
ei
/* pllc[14]=1 selects the PLL.
/* Globally re-enable interrupts.
*/
*/
.
.
.
/* user code with CLK = 100 MHz
*/
pllc=0xa9f2
powerc=0x1c1f
2*nop
ioc=0x0040
alf=0x8000
nop
nop
nop
...
pllc=0xe9f2
powerc=0x0000
2*nop
ioc=0x0000
/* Prepare for standby - deselect PLL,
/* turn off peripherals and select slow clock.
/* Wait for it to take effect.
/* Hold CKO low.
/* Set AWAIT bit (stop core clock; interrupt logic
/* active.) nops needed for bedtime execution.
/* Reduced standby power plus PLL power consumed.
/* Interrupt wakes up the core.
/* User code executes here.
/* Reselect the PLL - PLL already locked.
/* Turn off slow clock and turn peripherals back on.*/
/* Wait for it to take effect.
/* CKO is free-running.
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
_standby:
cont:
*/
*/
1. The program exits low-power standby mode when any enabled interrupt occurs. Therefore, it is assumed that interrupts are globally enabled
and at least one interrupt is individually enabled.