
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
73
Software Architecture
(continued)
Instruction Set Quick Reference
(continued)
Table 32. Instruction Set Summary
(continued)
Special Function Group
(continued)
if
CON
aDE=abs(aSE)
ifc
CON aDE=abs(aSE)
if
CON
aDEh=aSEh+1
ifc
CON aDEh=aSEh+1
if
CON
aDE=aSE+1
ifc
CON aDE=aSE+1
if
CON
aDE=
y,pE
ifc
CON aDE=
y,pE
if
CON
aDE=
–y,–pE
ifc
CON aDE=
–y,–pE
if
CON
aDE=aSE<<
1,2,4,8,16
ifc
CON aDE=aSE<<
1,2,4,8,16
ALU Group
aD=aS OP
aTE,pE
aD=
aTE,pE
–aS
aD=FUNC(aS,
aTE,pE
)
aS–
aTE,pE
aS&
aTE,pE
if CON
aDE=aSE OP
pE,y
if CON
aDE=aSE OP aTE
if CON
aDE=
pE,y
–aSE
if CON
aDE=FUNC(aSE,
pE,y
)
if CON
aDE=FUNC(aSE,aTE)
if CON
aSE–
pE,y
if CON
aSE&
pE,y
if CON
aSE–aTE
if CON
aSE&aTE
if CON
aDEE=aSEE
±
aTEE
if CON
aDE=aSE+aTE
aDE=aSE
h,l
OP IM16
§
aDE=IM16–aSE
h,l
aSE
h,l
–IM16
aSE
h,l
&IM16
X
C
is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-
tion types and can only be avoided by use of the cache.
For this transfer, the postincrement options
*rME
and
*rME––
are not available
for double-word loads.
§ The – (40-bit subtraction) operation is encoded as
aDE=aSE+IM16
with the IM16 value negated.
For conditional branch instructions, the execution time is two cycles if the branch is not taken.
The instruction performs the same function whether or not
near
(optional) is included.
§§ Not including the N instructions.
(F2E)
(F2E)
(F2E)
(F2E)
(F2E)
(F2E)
(F2E)
(F2E)
(F2E)
(F2E)
(F2E)
(F2E)
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlme
szlme
1
1
2
(F3)
(F3)
(F3)
(F3)
(F3)
(F3E)
(F3E)
(F3E)
(F3E)
(F3E)
(F3E)
(F3E)
(F3E)
(F3E)
(F3E)
(F3E)
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
szlm–
1
1
1
1
1
2
aDPE=aSPE
±
aTPE
else aDE=aSE–aTE
(F3 with immediate)
(F3 with immediate)
(F3 with immediate)
(F3 with immediate)
1
1
2
Instruction
Flags
szlme
Cycles
Out
Words
In