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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 20/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
20
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Interrupts and Trap
The DSP16210 supports the following interrupts and
traps:
I
15 hardware interrupts with three levels of user-
assigned priority.
I
64 software interrupts (
icall IM6
instruction).
I
The TRAP input pin. (The TRAP pin is configured as
an output only under JTAG control to support HDS
multiple-processor debugging.) By default, after
reset, the TRAP pin is configured as an input and is
connected directly to the core via the PTRAP signal.
If the TRAP pin is asserted, the core vectors to a
user-supplied trap service routine at location
vbase
+ 0x4.
Five pins of the DSP16210 are devoted to signaling
interrupt service status. The IACK pin goes high when
the core begins to service an interrupt or trap, and goes
low three internal clock (CLK) cycles later. Four pins,
VEC[3:0], carry a code indicating which of the inter-
rupts or trap is being serviced.
Table 4 on page 21
con-
tains the encodings used by each interrupt.
If an interrupt or trap condition arises, a sequence of
actions service the interrupt or trap before the
DSP16210 resumes regular program execution. The
interrupt and trap vectors are in contiguous locations in
memory, and the base (starting) address of the
352-word vector table is configurable in the
vbase
reg-
ister.
Table 4 on page 21
describes the vector table.
Assigning each interrupt and trap source to a unique
location differentiates selection of their service rou-
tines. When an interrupt or trap is taken, the core saves
the contents of
PC
and vectors execution to the appro-
priate interrupt service routine (ISR) or trap service rou-
tine (TSR).
There are 15 hardware interrupts with three levels of
user-assigned priority. Interrupts are globally enabled
by executing the
ei
(enable interrupts) instruction and
globally disabled by executing the
di
(disable inter-
rupts) instruction. The user assigns priorities and indi-
vidually disables (masks) interrupts by configuring the
inc0
and
inc1
registers. The
ins
register contains sta-
tus information for each interrupt. The
psw1
register
includes control and status bits associated with the
interrupt handler. When an interrupt is taken, the
pi
register holds the interrupt return address.
Software interrupts allow the testing of interrupt rou-
tines and their operation when interrupts occur at spe-
cific code locations. Programmers and system
architects can observe behavior of complex code seg-
ments when interrupts occur (e.g., multilevel subroutine
nesting, cache loops, etc.).
A trap is similar to an interrupt but has the highest pos-
sible priority. Traps cannot be disabled by executing a
di
instruction. Traps do not nest, i.e., a TSR cannot be
trapped. The state of the
psw1
register is unaffected by
traps. When a trap is taken, the
ptrap
register holds the
trap return address.
An interrupt or trap service routine can be either a four-
word entry in the vector table or a larger service routine
reached via a
goto
instruction in the vector table, in
either case. The service routine must end with a
tre-
turn
instruction for traps or an
ireturn
instruction for
interrupts. Executing
ireturn
globally enables inter-
rupts (executing
treturn
does not).
Interrupt Registers
The software interrupt and the traps are always
enabled and do not have a corresponding bit in the
ins
register. Other vectored interrupts are enabled in the
inc0
and
inc1
registers (
Table 5 on page 22
) and mon-
itored in the
ins
register (
Table 6 on page 22
). One of
three priority levels for each hardware interrupt can be
configured using two consecutive bits of
inc0
or
inc1
.
There are two reasons for assigning priorities to inter-
rupts.
I
Nesting interrupts, i.e., an interrupt service routine
can be interrupted by an interrupt of higher priority.
I
Servicing concurrent interrupts according to their pri-
ority.
The
ins
register indicates the pending status of each
interrupt. When set to 1, the status bits in the
ins
register indicate that an interrupt is pending. An
instruction clears an interrupt by writing a one to the
corresponding bit in the
ins
register (e.g.,
ins = IM20
).
Writing a zero to any bit leaves the bit unchanged. The
interrupts corresponding to the least significant bits of
ins
are given higher default priority
1
than the interrupts
corresponding to the most significant bits of
ins
. The
processor must reach an interruptible state (completion
of an interruptible instruction) before action is taken on
an enabled interrupt. An interrupt is not serviced if it is
not enabled.
1. Priority is primarily determined by programming the
inc0
and
inc1
registers (
Table 5 on page 22
). For interrupts with the same
programmed priority, the position of their corresponding bits in
ins
determine their relative priority. For example, the EOFE and
EIFE interrupts (
ins
[12:11]) default to a higher priority than
EOBE and EIBF (
ins
[15:14]).
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