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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 47/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
47
Hardware Architecture
(continued)
Modular I/O Units (MIOUs)
(continued)
DMA Input Flow Control
(continued)
The ILEN
0,1
_UP command is an accumulating operation that permits I/O and core processing to be overlapped
and the logical buffer structure to be enforced by synchronizing MIBF
0,1
interrupts. If ILEN
0,1
_UP operations
(L1 and L2) are issued without synchronizing with an intervening MIBF
0,1
, the subsequent MIBF
0,1
interrupt
occurs when the (L1 plus L2) samples are processed.
The assertion of MIBF
0,1
does not necessarily imply that all input buffer resources are exhausted (as IBF does
for the SSIO). MIBF
0,1
is a flow control signal and does not affect MIOU
0,1
processing of input or output data.
DMA Output Flow Control
The core and MIOU
0,1
cooperate to manage the output flow by updating
OLEN
0,1
. Typically, software initial-
izes
OLEN
0,1
with the logical buffer size (number of samples), L1, of the first input transaction. When
MOBE
0,1
is asserted, software processes the first logical buffer (using L1) and issues an OLEN
0,1
_UP com-
mand with a parameter equal to the number of samples in the next logical buffer (L2). MIOU
0,1
and core pro-
cessing are concurrent, so the MIOU
0,1
fills the new buffer while the first buffer is processed by the core.
MIOU
0,1
produces a busy flag MBUSY
0,1
that indicates that it has unfinished output operations pending.
When this signal is cleared, all scheduled output transfers are complete and the core can safely enter low-power
standby mode. MIOU0 produces the software-visible MBUSY0 condition flag in
alf
register bit 4. MIOU1 produces
the software-visible MBUSY1 condition flag in
alf
register bit 5. (See
Table 37 on page 85
and
Table 42 on
page 91
.)
MIOU Performance
The MIOU supports a maximum throughput of a single 16-bit input word or a single 16-bit output word every four
DSP clock periods (maximum sustained throughput of CLK/4 words/second).
External timing constraints may not permit an external device to drive at these rates. In addition, this maximum rate
is reduced by core-MIOU IORAM collisions.
Powering Down an MIOU
An MIOU remains powered up and operational in low-power standby mode. (Its clock remains running and is not
stopped when AWAIT (
alf
[15]) is set.)
The program powers down an MIOU by setting MIOU0 (bit 2) or MIOU1 (bit 3) of the
powerc
register (see
Table 65
on page 106
). If an MIOU is powered down, then some of its internal state information is lost. Therefore, an MIOU
should be powered down only under one of the following two conditions:
1. The MIOU is not required in the application.
2. After powering down the MIOU and then powering it up, the application reinitializes the MIOU by executing an
MIOU RESET command (see
MIOU Commands beginning on page 43
).
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