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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 122/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
122
DRAFT COPY
Lucent Technologies Inc.
Signal Descriptions
(continued)
System Interface and Control I/O Interface
System Interface
The system interface consists of the clock, interrupt,
and reset signals for the processor.
RSTB — Device Reset:
Negative assertion input. A
high-to-low transition causes the processor to enter the
reset state. See
Reset on page 18
for details.
CKI — Input Clock:
The CKI input buffer drives the
internal clock (CLK) directly or drives the on-chip PLL
(see
Clock Synthesis beginning on page 56
). The PLL
allows the CKI input clock to be at a lower frequency
than the internal clock.
STOP — Stop DSP Clocks:
Negative assertion input.
A high-to-low transition synchronously stops the inter-
nal clock, leaving the processor in a defined state.
Returning the pin high synchronously restarts the inter-
nal clock to continue program execution from where it
left off without any loss of state. This hardware feature
has the same effect as setting the NOCK bit in the
powerc
register (see
Table 65 on page 106
).
CKO — Programmable Clock Output:
Buffered out-
put clock with options programmable via the
ioc
regis-
ter (see
Table 54 on page 99
). The selectable CKO
options are as follows:
CLK: A free-running output clock at the frequency of
the internal clock.
CLKE: Clock at the frequency of the internal clock
held high during low-power standby mode (high
when AWAIT (
alf
[15]) is high).
CKI: Clock input pin.
ZERO: A constant logic 0 output.
ONE: A constant logic 1 output.
INT[3:0] — External Interrupt Requests:
Positive
pulse assertion inputs. Hardware interrupt inputs to the
DSP16210. Each is enabled via the
inc0
register.
When enabled and asserted properly with no equal- or
higher-priority interrupts being serviced, each cause
the processor to vector to the memory location
described in
Table 4 on page 21
. If an INT pin is
asserted for at least the minimum required assertion
time (see t22 on page 145), the corresponding external
interrupt request is recorded in the
ins
register. If an
INT pin is asserted for less than the minimum required
assertion time, the corresponding interrupt request
might or might not be recorded in the
ins
register. To
avoid erroneous extra entries into the INT interrupt ser-
vice routine (ISR), an INT pin must be deasserted at
least three instruction cycles before the terminating
ire-
turn
instruction for the associated ISR is executed.
When both INT0 and RSTB are asserted, all output
and bidirectional pins (except TDO, which 3-states by
JTAG control) are put in a 3-state condition.
VEC[3:0] — Vectored Interrupt IDs:
Outputs. These
four pins indicate which interrupt is currently being ser-
viced by the device.
Table 4 on page 21
shows the
code associated with each interrupt condition.
VEC[3:0] are multiplexed with IOBIT[7:4] (see
Pin Mul-
tiplexing on page 13
). VEC0 corresponds to IOBIT7,
VEC1 corresponds to IOBIT6, VEC2 corresponds to
IOBIT5, and VEC3 corresponds to IOBIT4. VEC[3:0]
defaults to 0xF (all ones) if no interrupt or trap is cur-
rently being serviced.
IACK — Interrupt Acknowledge:
Positive assertion
output. IACK signals when an interrupt is being ser-
viced by the DSP16210. IACK is asserted for three
DSP clock cycles.
TRAP — TRAP/Breakpoint Indication:
Positive pulse
assertion input/output. When asserted, the processor is
put into the trap condition, which normally causes a
branch to the location
vbase
+ 4. Although normally an
input, the pin can be configured as an output by the
HDS block. As an output, the pin can be used to signal
an HDS breakpoint in a multiple processor environ-
ment.
Control I/O Interface
The control I/O interface is used for status and control
operations provided by the BIO unit.
IOBIT[7:0] —
BIO Signals:
Input/Output. Each of
these pins can
be independently configured as either
an input or an output. As outputs, they can be inde-
pendently set, toggled, or cleared. As inputs, they can
be tested independently or in combinations for various
data patterns. IOBIT[7:4] are pin multiplexed with the
VEC[3:0] pins (see
Pin Multiplexing on page 13
). Set-
ting the EBIO bit in the
ioc
register (bit 8) provides a full
8-bit BIO interface at the associated pins.
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