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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 60/173頁(yè) |
| 文件大小： | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
60
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Clock Synthesis
(continued)
Phase-Lock Loop (PLL) Programming Example
The example in this section assumes the CKI input clock frequency is 10 MHz and the desired internal clock fre-
quency is 100 MHz.
Table 30
illustrates the calculation of the M and N values and the corresponding Mbits[4:0]
and Nbits[2:0] values to be programmed into
pllc
(see
Table 64 on page 105
).
Table 30. Example Calculation of M and N
CKI Input Frequency
CLK Frequency
PLL Frequency
PLL Ratio
The following code segment illustrates the programming, enabling, and selecting of the PLL according to the values
in
Table 30
, assuming the PLL is initially disabled and deselected:
di
pllc = 0xa9f2
if lock goto locked /* Wait until LOCK flag is set
goto wait
/* While waiting, CLK = CKI = 10 MHz
pllc = 0xe9f2
/* Select PLL clock - no other change to pllc
ei
/* Re-enable interrupts
goto start
/* User's code, now running at 100 MHz
/* Disable interrupts for PLL lock (recommended)
/* Enable PLL, keep it deselected, program M, N, LF */
*/
wait:
*/
*/
*/
*/
*/
locked:
Examples of programming the PLL and using the various power management modes are included in
Power Man-
agement beginning on page 61
.
Phase-Lock Loop (PLL) Frequency Accuracy and Jitter
Although the average frequency of the PLL output has almost the same relative accuracy as the input clock, noise
sources within the DSP produce jitter on the PLL clock. The PLL is guaranteed to have sufficiently low jitter to oper-
ate the DSP. However, if the PLL clock is driven off the device onto the CKO pin, do not apply this clock to jitter-
sensitive devices. See
Table 87 on page 139
for the input jitter requirements for the PLL.
Phase-Lock Loop (PLL) Power Connections
The PLL has its own power and ground pins, V
DDA
and V
SSA
. Because the PLL contains analog circuitry, V
DDA
and
V
SSA
are sensitive to supply noise. To filter supply noise, connect a dedicated decoupling capacitor from V
DDA
to
V
SSA
. Depending on the characteristics of the supply noise in the particular application, a series ferrite bead or
resistor might also be needed. V
SSA
can be connected directly to the main ground plane. This recommendation is
subject to change and can be modified for specific applications depending on the characteristics of the supply
noise.
f
CKI
f
CLK
f
PLL
M/2N
M/N
M
N
10 MHz
100 MHz
100 MHz
10
20
20
1
Mbits[4:0] = M – 2 = 18 = 0x12
Nbits[2:0] = 7 = 0x7
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