參數(shù)資料
型號(hào)： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號(hào)處理器
文件頁數(shù)： 123/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
123
Signal Descriptions
(continued)
External Memory Interface
The EMI is used to interface the DSP16210 to external
memory and I/O devices. It supports read/write opera-
tions from/to X- and Y-memory spaces. The interface
supports four external memory segments (EROM,
ERAMHI, ERAMLO, and IO). The access times for
these segments are programmable in the
mwait
regis-
ter (see
Table 58 on page 101
).
AB[15:0] — External Memory Address Bus:
Output.
This 16-bit bus supplies the address for read or write
operations to the external memory or I/O. If external
memory is not being accessed, AB[15:0] retains its
value from the last valid external access.
DB[15:0] — External Memory Data Bus:
Input/Out-
put. This 16-bit bidirectional data bus is used for read
or write operations to the external memory or I/O. Write
data activation can be delayed by setting WDDLY (bit
10 of the
ioc
register).
EXM — External Memory Boot Select:
Input. This
signal is latched into the device on the rising edge of
RSTB. The value of EXM latched in determines which
memory region (EROM/IROM) is used when the
DSP16210 boots up in response to a device reset. If
EXM is low, the DSP16210 boots from IROM. If EXM is
high, the DSP16210 boots from EROM.
RWN — EMI Read/Write Not Indicator:
Output. When
a logic 1, this pin indicates that the data memory (Y)
access is a read operation. When a logic 0, it indicates
that the memory access is a write operation. This sig-
nal can be advanced by setting RWNADV (bit 3 of
ioc
).
EROM — External ROM Enable:
Negative assertion
output. When asserted, this signal indicates an access
(either X or Y) to the EROM segment (see
Figure 5 on
page 25
or
Figure 6 on page 26
). The leading edge is
delayed by one CLK phase by setting the DENB0 field
(bit 0 of
ioc
).
ERAMHI — External RAM High Enable:
Negative
assertion output. When asserted, this signal indicates a
Y access to the external ERAMHI segment (see
Figure 6 on page 26
). The leading edge is delayed by
one CLK phase by setting the DENB1 field (bit 1 of
ioc
).
ERAMLO — External RAM Low Enable:
Negative
assertion output. When asserted, this signal indicates a
Y access to the external ERAMLO segment (see
Figure 6 on page 26
). The leading edge is delayed by
one CLK phase by setting the DENB1 field (bit 1 of
ioc
).
IO — External I/O Enable:
Negative assertion output.
When asserted, this signal indicates an access to the
external data memory-mapped IO segment (see
Figure 6 on page 26
). The leading edge is delayed by
one CLK phase by setting the DENB2 field (bit 2 of
ioc
).
ERAM — External RAM Enable:
Negative assertion
output. When asserted, this signal indicates an access
to either the ERAMHI or ERAMLO external memory
segments. The leading edge is delayed by one CLK
phase by setting the DENB1 field (bit 1 of
ioc
).
READY — External Memory Access
Acknowledge:
Negative assertion input. The READY
input pin permits an external device to extend the
length of an EMI access cycle. The READY pin can be
used if an external memory requires an access time
greater than 15 cycles, the maximum value program-
mable in
mwait
. The DSP16210 internally synchro-
nizes the READY pin to the processor clock (CLK).
READY must be asserted at least five cycles (plus a
setup time) prior to the end of the external memory
operation. The DSP16210 adds the number of cycles
that READY is asserted to the access time. The appro-
priate I/O access time field in
mwait
must be four or
greater, or the READY pin is ignored.
ESIO Interface
The enhanced serial input/output port (ESIO) is a pro-
grammable, hardware-managed, double-buffered
input/output port designed to support glueless multi-
channel I/O processing on a TDM (time-division multi-
plex) highway. The ESIO communicates the input and
output buffer status to the core using input buffer full
(EIBF), output buffer empty (EOBE), input frame error
(EIFE), output frame error (EOFE), and output collision
(ECOL) interrupts. The ESIO external pin signals are
described below:
EDI — ESIO Data Input:
Serial data is latched on the
falling edge of EIBC. Input is at CMOS level and has
typically 0.7 V hysteresis.
EIFS — ESIO Input Frame Sync:
Input. EIFS defines
the beginning of a new input frame (frame mode) or
serial data packet (simple mode). To suit a variety of
system design requirements, EIFS can be internally
inverted and/or delayed for one bit clock (under the
control of bits ISLEV and ISDLY of the
ICR
register) to
produce the internal input frame sync, IFS. Input is at
CMOS level and has typically 0.7 V hysteresis.
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