參數(shù)資料
型號(hào)： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號(hào)處理器
文件頁數(shù)： 128/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
128
DRAFT COPY
Lucent Technologies Inc.
DSP16210 Boot Routines
(continued)
Commands
(continued)
Table 81. Command Encoding for Boot Routines
(continued)
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0x0111
PHIF16
EROM
(64K)
8-bit
8-bit
Motorola
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
—
1 word
Intel
Motorola
8-bit
16-bit
No
Intel
Motorola
16-bit
16-bit
No
Intel
Motorola
0x0222
8-bit
8-bit
—
Intel
Motorola
8-bit
16-bit
No
Intel
Motorola
16-bit
16-bit
No
Intel
Motorola
0x0444
8-bit
8-bit
—
Intel
Motorola
8-bit
16-bit
No
Intel
Motorola
16-bit
16-bit
No
Intel
Motorola
0x0FFF
8-bit
8-bit
—
Intel
Motorola
8-bit
16-bit
No
Intel
Motorola
16-bit
16-bit
No
Intel
Command
Code
mwait
Setting
Function/Download
Download
From
Download
To
Configuration
PHIF16
Mode
MIOU0
DMA
Block
External
Bus
Logical
Transfer
PODS/
PDS
Byte-
Swapping
The boot routine configures the PHIF16 by writing to the
PHIFC
register. Specifically, the external bus configuration, logical transfer size, and
byte swapping are controlled by the PMODE and PCFIG fields, the mode is controlled by the PSTROBE field, and the PODS/PDS active-
low/high configuration is controlled by the PSTRB field. After the download is complete, the boot routine returns the PHIF16 to its initial state
(configures it for Intelmode with an 8-bit external bus and 8-bit logical transfers).
This is the size of each input DMA transfer that the boot routine directs the MIOU0 to perform without core intervention. MIOU0 performs
input DMA from the PHIF16 block. The boot routine configures the input block size by programming the
ILEN0
register.
§ The first 60 Kword locations of the segment are copied into the DPRAM.
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