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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 27/173頁(yè) |
| 文件大小： | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
27
Hardware Architecture
(continued)
Memory Maps
(continued)
The addresses shown in Figures
5
and
6
correspond to
the 20-bit core address buses (XAB for the XMAP and
YAB for YMAP0/YMAP1). For external memory
accesses, these 20-bit addresses are truncated to
16 bits and the external enable pins (EROM, ERAMHI,
ERAMLO, and IO) differentiate the 64K segment being
accessed. For IORAM accesses, these 20-bit
addresses are truncated to 10 bits.
Boot from External ROM
The EXM pin determines from which memory region
(EROM or IROM) the DSP16210 executes code follow-
ing a device reset. EXM is captured by the rising edge
of RSTB. If the captured value of EXM is one, the
DSP16210 boots from external ROM (EROM—core
address 0x80000). Otherwise, the DSP16210 boots
from internal IROM (core address 0x20000). See
DSP16210 Boot Routines beginning on page 126
for
details on booting from IROM.
Data Memory Map Selection
The DSP16210 data memory map selection is based
on the value of the WEROM field (bit 4) in the
ioc
regis-
ter (
Table 54 on page 99
). If WEROM is set to 0, the
YMAP0 data memory map is selected. If WEROM is
set to 1, the YMAP1 data memory map is selected. If
WEROM is 1, all ERAMLO accesses are redirected to
the EROM segment.
External Memory Interface (EMI)
The external memory interface (EMI) manages off-chip
memory and on-chip IORAM memory and ESIO stor-
age, collectively referred to as EMI storage.
The EMI multiplexes the two sets of core buses
(XAB/XDB and YAB/YDB) onto a single set of external
buses—a 16-bit address bus (AB) and 16-bit data bus
(DB). It also multiplexes the two sets of core buses
onto a single set of internal EMI buses—a 10-bit
address bus (EAB) and a 16-bit data bus (EDB)—for
access to the IORAM and ESIO storage. The EMI auto-
matically translates 32-bit XDB/YDB accesses into two
16-bit DB/EDB accesses and vice versa. If an instruc-
tion accesses EMI storage from both the X side and Y
side, the EMI performs the X access first followed by
the Y access and the core incurs a conflict wait-state.
The EMI accesses four external memory segments—
ERAMHI, ERAMLO, EROM, and IO.
Two control registers are encoded by the user to define
the operation of the EMI. Bits 14—0 in
mwait
(
Table 58 on page 101
) and bits 10 and 7—0 in
ioc
(
Table 54 on page 99
) apply to the EMI. These pro-
grammable features give the designer flexibility in
choosing among various external memories.
Latency for Programming mwait and ioc Registers
There is a two instruction cycle latency between an
instruction that updates either
ioc
or
mwait
and avail-
ability of the new value in the EMI. It is recommended
that two
nop
s (or other instructions that do not access
external memory) follow each
ioc
or
mwait
update
instruction. See the example below:
mwait=0x0222/* Modify mwait
2*nop
/* Wait for latency
a0=*r0
/* OK to perform EMI read */
*/
*/
For write operations the EMI buffers the data (see
Functional Timing beginning on page 29
), software
must verify that all pending external write operations
have completed before modifying
ioc
or
mwait
. Software ensures that all memory operations
have completed by executing an external memory read
operation. After the read operation is completed, it is
safe to modify
ioc
or
mwait
. See the code segment
below for an example:
*r1++=a1
a0=*r2
mwait=0x0222/* Safe to modify mwait.
2*nop
/* Wait for mwait latency. */
/* EMI write.
/* Dummy EMI read.
*/
*/
*/
Note:
For the EMI to function properly, the application
program
must
adhere to the latency restrictions
presented above.
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