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參數(shù)資料
| 型號： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號處理器 |
| 文件頁數(shù)： | 131/173頁 |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
131
DSP16210 Boot Routines
(continued)
Commands
(continued)
Table 81. Command Encoding for Boot Routines
(continued)
0x70
—
Test internal CACHE (62 words) memory segment—write result word to
ar3
(0x0FAB for passed and
0x0BAD for failed).
Test external 64K ERAMLO memory segment—write result word to
ar3
(0x0FAB for passed and 0x0BAD for
failed).
0x31
0x71
0xB1
0xF1
0x33
0x73
0xB3
0xF3
0x1A
0x5A
0x9A
0xDA
0x38
0x78
0xB8
0xF8
0x3F
0x7F
0xBF
0xFF
0x2C
0x0111
0x0222
0x0444
0x0FFF
0x0111
0x0222
0x0444
0x0FFF
0x0111
0x0222
0x0444
0x0FFF
0x0111
0x0222
0x0444
0x0FFF
0x0111
0x0222
0x0444
0x0FFF
—
Test external 64K ERAMHI memory segment—write result word to
ar3
(0x0FAB for passed and 0x0BAD for
failed).
Test external 128K ERAMLO and ERAMHI memory segments—write result word to
ar3
(0x0FAB for passed
and 0x0BAD for failed).
Test external 64K EROM memory segment—write result word to
ar3
(0x0FAB for passed and 0x0BAD for
failed).
Test external 64K IO memory segment—write result word to
ar3
(0x0FAB for passed and 0x0BAD for failed).
Perform checksum on 60K DPRAM. Write the checksum result (two 16-bit words) to the PHIF16 port in Intel
16-bit mode. The purpose of the checksum routine is to check that code has been downloaded properly into
the DPRAM segment. After the host reads the two checksum words, return the PHIF16 to Intel8-bit mode
and write the handshake byte 0xED to the PHIF16 port.
Perform checksum on 64K EROM. Write the checksum result (two 16-bit words) to the PHIF16 port in Intel
16-bit mode. The purpose of the checksum routine is to check that code has been downloaded properly into
the EROM segment. After the host reads the two checksum words, return the PHIF16 to Intel8-bit mode
and write the handshake byte 0xED to the PHIF16 port.
0x2D
0x6D
0xAD
0xED
0x15
0x0111
0x0222
0x0444
0x0FFF
—
Copy word in
ar3
(result of the previously run memory test—0x0FAB for passed and 0x0BAD for failed) to the
PHIF16 port in Motorola 16-bit mode with active-high PDS.
Copy word in
ar3
(result of the previously run memory test—0x0FAB for passed and 0x0BAD for failed) to the
PHIF16 port in Motorola 16-bit mode with active-low PDS.
Copy word in
ar3
(result of the previously run memory test—0x0FAB for passed and 0x0BAD for failed) to the
PHIF16 port in Intel16-bit mode.
Copy word in
ar3
(result of the previously run memory test—0x0FAB for passed and 0x0BAD for failed) to the
PHIF16 port in Motorola 16-bit mode with active-high PDS.
0x55
—
0x95
—
0xD5
—
Command
Code
mwait
Setting
Function/Download
Download
From
Download
To
Configuration
PHIF16
Mode
MIOU0
DMA
Block
External
Bus
Logical
Transfer
PODS/
PDS
Byte-
Swapping
The boot routine configures the PHIF16 by writing to the
PHIFC
register. Specifically, the external bus configuration, logical transfer size, and
byte swapping are controlled by the PMODE and PCFIG fields, the mode is controlled by the PSTROBE field, and the PODS/PDS active-
low/high configuration is controlled by the PSTRB field. After the download is complete, the boot routine returns the PHIF16 to its initial state
(configures it for Intelmode with an 8-bit external bus and 8-bit logical transfers).
This is the size of each input DMA transfer that the boot routine directs the MIOU0 to perform without core intervention. MIOU0 performs
input DMA from the PHIF16 block. The boot routine configures the input block size by programming the
ILEN0
register.
§ The first 60 Kword locations of the segment are copied into the DPRAM.
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